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參數(shù)資料
| 型號： | STLC5048 |
| 廠商： | 意法半導體 |
| 元件分類： | Codec |
| 英文描述： | FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 完全可編程四通道解碼器和過濾器 |
| 文件頁數(shù)： | 11/45頁 |
| 文件大?。?/td> | 371K |
| 代理商： | STLC5048 |
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STLC5048
In the multiple byte instructions the first one specifies the command or the register address and the access type
(Read or Write).
The following bytes contain the data to be loaded into the internal RAM (on CI wire) or carry out the RAM content
(on CO wire) depending on the R/W bit of the first byte. CO wire is normally in High Impedance and goes to low
impedance only after the first byte in case of Read operation. This allows to use a common wire for both CI/CO.
CS, normally High, is set Low during the transmission/reception of a byte, lasting 8 CCLK pulses. Between two
consecutive access the CS must be set high.
The CCLK can be a continuos or a gated clock.
The result of any instruction (read/write operation), if negative, can generate an interrupt (maskable). The inter-
rupt register (INT) contains the cause information of the generated interrupt and it is cleared every time that it
is read.
Depending on the instruction specified in the first byte, the STLC5048 waits a defined number of data bytes. If
the STLC5048 doesn't receive the data byte within a predefined period specified by means of T_OUT command,
an internal time out rejects the instruction. The time-out time is verified between two consecutive MCU interface
access (between the falling edge of the CS and the following rising edge).
This feature is used to verify the synchronisation of the MCU interface: however it can be disabled if not desired
(see T_OUT reg description). To check this synchronisation is provided a specific register (SYNCK) that returns
always a predefined value: if the returned value is different the MCU interface is in out of sync state (the device
is waiting a data byte while the MCU is writing an address or vice versa). In this case, it is possible to realign it
by means of the execution of a specific single byte instruction (REACOM) from 1 to 53 times, depending on the
instructions.
Every time an illegal operation (access to not allowed address, time-out violation or clock pulse different than 8
inside a CS active) is performed the MCU interface is put on an error state: to resume it from this state a single
REACOM instruction can be used.
Anyway after a REACOM instruction a successful SYNC instruction guarantees the correct synchronisation.
One additional wire provided to the control interface is an open drain interrupt output (INT) that goes low when
a change of status is detected on the I/O pins or other interrupt source are active (see INT register). INT is au-
tomatically reset after reading of the register corresponding the cause that has generated the interrupt (see INT
register description).
A particular register (COMEN) allows to enable a command on different channel at the same time. Every time
a command operation is performed at least one channel must be enabled in this register.
This feature is useful when all channels must be configured in the same condition. When a command is used
to perform a read operation only one channel can be enabled at the same time.
To check the configuration of the device a checksum value is provided. This value is calculated on all coefficient
parameters entered (coefficients of KD, AFE_CFF, GRX, GTX, RFC, XFC, BFC, ZFC blocks; see CKSUM reg-
ister description). Two commands are required to get this value: the first one (CKSTART) starts the internal
checksum calculation, the second one (CKSUM) returns the calculated value. Between this two commands no
other operation are allowed. The checksum value is available within 400us the CKSTART command.
Coefficient checksum is defined by this algorithm:
X
16
+ X
12
+ X
5
+ 1
This algorithm guarantees a fault coverage of 1 - 2
-16
.
PROGRAMMING THE DEVICE
After the power up, the filters and gain blocks can be programmed also with all the channels set in Power Down.
In this case the PDR bit of the COMEN register must be set to 0.
With the proper setting of the COMEN register, the commands can be applied to more than one channel at the
same time.
To read the coefficient values loaded in the RAM, only one channel per time must be enabled in the COMEN
register.
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PDF描述 |
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| STLC5411FN | 2B1Q U INTERFACE DEVICE |
| STLC5411P | 2B1Q U INTERFACE DEVICE |
| STLC5411 | 2B1Q U Interface Device(2BIQ U接口裝置) |
| STLC5412 | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| STLC5048TR | 功能描述:接口—CODEC Prog 4-Ch CODEC/Filt RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| STLC5411 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
| STLC5411CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
| STLC5411FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
| STLC5411P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
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