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STLC5048
PIN DESCRIPTION
(continued)
DIGITAL PIN DESCRIPTION
No.
Name
Type
Description
27
54
M0
M1
DI
Mode Select.
M1 M0 Mode select
0 0 Reset Status
1 0 Normal Operation
0 1 Not Allowed
1 1 Not Allowed
14
FS
DI
Frame Sync. Pulse. A pulse or a square waveform with an 8kHz
repetition rate is applied to this pin to define the start of the receive
and transmit frame. Effective start of the frame can be then shifted of
up to 7 clock pulses independently in receive and transmit directions
by proper programming of the PCMSH register.
13
MCLK
DI
Master Clock Input.
Four possible frequencies can be used:
1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz.
The device automatically detect the frequency applied.
This signal is also used as bit clock and it is used to shift data into
and out of the DRA/B and DXA/B pins.
12
TSXA
ODO
Transmit Time Slot (open drain output, 3.2mA). Normally it is floating
in high impedance state except when a time slot is active on the DXA
output. In this case TSXA output pulls low to enable the backplane
line driver.
11
DXA
DTO
Transmit PCM interface A. It remains in high impedance state except
during the assigned time slots during which the PCM data byte is
shifted out on the rising edge of MCLK.
10
DRA
DI
Receive PCM interface A. It remains inactive except during the
assigned receive time slots during which the PCM data byte is shifted
in on the falling edge of MCLK.
24
IO5
DIO
General control I/O pin #5. Can be programmed as input or output via
DIR register. Depending on content of CONF register can be a static
input/output or a dynamic input/output synchronised with the CSn
output signals controlling the SLICs.
62
IO6
DIO
General control I/O pin #6. (see IO5 description).
61
IO7
DIO
General control I/O pin #7. (see IO5 description).
60
IO8
DIO
General control I/O pin #8. (see IO5 description).
59
IO9
DIO
General control I/O pin #9. (see IO5 description).
58
IO10
DIO
General control I/O pin #10. (see IO5 description).
57
IO11
DIO
General control I/O pin #11. (see IO5 description).
19
IO0
DIO
General control I/O pin #0. (see IO5 description).
20
IO1
DIO
General control I/O pin #1. (see IO5 description).
21
IO2
DIO
General control I/O pin #2. (see IO5 description).
22
IO3
DIO
General control I/O pin #3. (see IO5 description).
23
IO4
DIO
General control I/O pin #4. (see IO5 description).