- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380765 > STLC5048 (意法半導(dǎo)體) FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER PDF資料下載
參數(shù)資料
| 型號： | STLC5048 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 完全可編程四通道解碼器和過濾器 |
| 文件頁數(shù)： | 8/45頁 |
| 文件大?。?/td> | 371K |
| 代理商： | STLC5048 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
STLC5048
8/45
FUNCTIONAL DESCRIPTION (continued)
RINGING STATE
This state can be used during the ringing phase in order to transmit a low frequency ringing signal (25-50 Hz).
In order to obtain a 1 Vrms ringing signal at VFRO output a digital signal DR equal to -0.78dBm0 must be pro-
vided.
This state means B, Z, X, KD and KA blocks equal to open circuits and the R block configured in order to obtain
the maximum gain at the frequency of 25-50 Hz. During the ringing state if the TX time slot is enabled the idle
PCM code is forced to DX.
To switch to this state, a bit (FR0..3) in the COEFST register must be set for every channel.
The programmed values for the previous blocks become active only when the FR and FD bits are reset.
If both FR and FD bits of a channel are set, the selected coefficient will be those of the Ringing State.
IMPEDANCE SYNTHESYS
The impedance synthesis is performed by fully digital filters (Z and KD) and by an analog path (KA).
The Z, KD and KA filters report to the receive path the feedback signal coming from the transmit path. The co-
efficients of the Z, KD and KA filters are programmed via the ZFC, KD and AFE_CFF commands respectively.
ECHO CANCELING
The trans-hybrid balance is performed by the digital programmable filter B.
The B filter reports to the transmit path the signal coming from the receive path. The coefficient of the B filter
are programmed via the BFC command.
Figure 2. Transmit path.
TRANSMIT PATH
The transmit section input consist of the input amplifier, the A/D converter, the equalization filter X, the gain
block GX, the encoder and the channel filters (LPX and HPX).
The input amplifier is provided of a programmable gain with a typical input impedance of 1M
. The amplifier
gain can be programmed with two different values (0dB, +3.52dB) by means of the TXG Register.
VFXI input must be AC coupled to the signal; the voltage swing allowed is 1.4Vpp when the preamplifier gain is
set to 0dB and 0.93Vpp when the gain is 3.52dB; higher levels must be reduced through proper dividers.
Following the input amplifier the signal is converted into digital domain and a X filter block is programmed to
equalise together with the HPX and LPX filters the frequency response. The coefficients of the X filter are pro-
grammed via the XFC command.
A gain block (GX) allows to set the transmit level in a 30dB range, with steps <0.01dB. This block can be pro-
grammed via the GTX command.
DX
TXG
VFXI
1M
AGND
Σ
CONV.
GXO
A/
μ
GX
for TXG=0dB; GX=0dB (FF)
61mVms => 0dBm0
D00TL469
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STLC5411FN | 2B1Q U INTERFACE DEVICE |
| STLC5411P | 2B1Q U INTERFACE DEVICE |
| STLC5411 | 2B1Q U Interface Device(2BIQ U接口裝置) |
| STLC5412 | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
| STLC5412FN | 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STLC5048TR | 功能描述:接口—CODEC Prog 4-Ch CODEC/Filt RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| STLC5411 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
| STLC5411CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
| STLC5411FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
| STLC5411P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。