
STLC5048
12/45
SLIC CONTROL INTERFACE
The device provides 12 I/O pins plus 4 CS signals. The interface can work in dynamic or static mode: it can be
selected by means of STA bit of the CONF register.
I
Dynamic Mode: the I/O pins are configured as input or output by means of DIR register. The CS signals
are used to select the different SLIC interface. In this case the I/O pin can be multiplexed. The data
loaded from SLIC #n via I/O pins configured as input can be read in the DATAn register. The data written
in a DATAn register will be loaded on the I/O pins configured as output when the Csn signal will be
active.
I
Static Mode: The CS signal can be used as I/O pins. They can be configured as input or output I/O by
means of DATA1 register. The data corresponding to the CS signal can be read or written by means of
DATA2 register. All data related to the other I/O pins can be read or written by means of DATA0 register.
DC SLIC PROGRAMMABILITY
Three additional pins are used to select the On-Hook/Off-Hook detection threshold and the line card limitation
of the STLC3080 SLIC. This two values are programmed by ILIM and ITH registers. The programmation of
these two registers must be done before the filter coefficients download.
The VBG input pin must be connected to the IREF pin of the STLC3080.
When the L3235N is used in kit with STLC5048 the ILIM, ITH and VBG pin must be not connected.
BUILT IN TEST
By means of TONEG register it is possible to inject a tone of variable frequency (25Hz, 1 and 3KHz) and 0dBm0
amplitude into the receive path, replacing any signal coming from the PCM interface. This test can be performed
on every channel.
Setting the proper bit of the PCMCOM register is also possible to read/write the PCM data coming from the
transmit path via the MCU interface (PCMRD/PCMWD registers). This feature can be enabled only on one
channel per time.
These two features can be used to test the line interface operation.
REGISTER ADDRESSES
Addr
Name
Description
00h
DIR-L
I/O Direction (bit 7-0)
01h
DIR-H
I/O Direction (bit 11-8)
02h
DATA0-L
I/O Data ch#0 (bit 7-0)
03h
DATA0-H
I/O Data ch #0 (bit 11-8)
04h
DATA1-L
I/O Data ch#1 (bit 7-0)
05h
DATA1-H
I/O Data ch #1 (bit 11-8)
06h
DATA2-L
I/O Data ch#2 (bit 7-0)
07h
DATA2-H
I/O Data ch #2 (bit 11-8)
08h
DATA3-L
I/O Data ch#3 (bit 7-0)
09h
DATA3-H
I/O Data ch #3 (bit 11-8)
0Ah
PCHK-A
Persistency Check Time for input A
0Bh
PCHK-B
Persistency Check Time for input B
10h
INT
Interrupt register