參數資料
型號： STLC5048
廠商： 意法半導體
元件分類： Codec
英文描述： FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述： 完全可編程四通道解碼器和過濾器
文件頁數： 9/45頁
文件大?。?/td> 371K
代理商： STLC5048
9/45
STLC5048
FUNCTIONAL DESCRIPTION (continued)
The needed TX gain can be set by proper programming of the GX block in combination with the TX amplifier.
Setting GTX=00h, the transmitted signal is muted and an idle PCM signal is generated on DX.
Concerning the CODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition,
via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits). In this case the signal sent
on the DX will take two adjacent PCM channels, proper care has to be taken in the time slot selection program-
ming (DXTS register).
The intrinsec non programmable gain GX0 set the TX path gain to 22.07dB. The absolute gain level (see elec-
trical characteristics) refers to this intrinsec gain.
RECEIVE PATH
The receive path of the STLC5048 consists of the decoder section, the gain block GR, the R filter, the channel
filters (LPR, HPR) the D/A converter and the output amplifier.
Concerning the DECODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition
via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits).
In this case the signal received on the DR input will take two adjacent PCM channels, proper care has to be
taken in the time slot selection programming (DRTS register).
The gain block GR is controlled by the GRX command allowing 30dB gain range in 0.01dB steps.
The R filter together the channel filters (LPR and HPR) performs the line equalization. The coefficients of the R
filter are programmed via the RFC command.
The signal is converted in the analog domain and amplified by the RX amplifier that can be programmed with
four different values (mute, 0dB, -6dB and -12dB) by means of RXG register.
Figure 3. Receive path.
VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent a DC current flow.
In order to get the best noise performances it is recommended to keep GRX value as close as possible to the
maximum (FFh) setting properly the additional attenuation by means of RXG.
The intrinsec non programmable gain GR0 set the RX path gain to -3.15dB. The absolute gain level (see elec-
trical characteristics) refers to this intrinsec gain.
PCM INTERFACE
The STLC5048 dedicates eight pins to the interface with the PCM highways.
MCLK represents the bit clock and is also used by the device as a source for the clock of the internal PLL.
Five possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels
PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating fre-
DR
RXG
VFRO
Σ
CONV.
GRO
A/
μ
GR
for RXG=0dB; GR=0dB
0dBm0 => -3dBm/
600
D00TL470
相關PDF資料
PDF描述
STLC5411FN 2B1Q U INTERFACE DEVICE
STLC5411P 2B1Q U INTERFACE DEVICE
STLC5411 2B1Q U Interface Device(2BIQ U接口裝置)
STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412FN 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
相關代理商/技術參數
參數描述
STLC5048TR 功能描述:接口—CODEC Prog 4-Ch CODEC/Filt RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
STLC5411 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE
STLC5411CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface
STLC5411FN 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE
STLC5411P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2B1Q U INTERFACE DEVICE
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*