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參數(shù)資料
| 型號： | STLC5048 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER |
| 中文描述： | 完全可編程四通道解碼器和過濾器 |
| 文件頁數(shù)： | 19/45頁 |
| 文件大?。?/td> | 371K |
| 代理商： | STLC5048 |
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STLC5048
Alarm Register (ALARM)
Addr=14h; Reset Value=01h
Read Only
POR=0: No Power On Reset is detected during operation.
POR=1: A Power On Reset is detected during operation.
The ALARM register is cleared after reading operation only if signals (alarm cause) are inactive.
Configuration Register (CONF)
Addr=20h; Reset Value=BFh
RES=0 Normal Operation
RES=1 Device Reset: I/0n and Csn are all inputs, DX is H.I. (equivalent to Hw reset).
LIN=0
A or
μ
law PCM encoding
LIN=1
Linear encoding (16 bits), two’s complement.
AMU=0
μ
law selection (all bits inverted)
AMU=1 A law selection (even bits inverted)
STA=0 CS0 to CS3 scan the four SLICs connected to the I/O control port, each CS has a 31.25
μ
s repetition
time.
STA=1I/O are static, CS0 to CS3 are configured as generic static I/O
PD3..0=0 Codec 3..0 is active
PD3..0=1 Codec 3..0 is in Power Down. When one codec is in Power Down the corresponding VFRO output is
set to AGND and the corresponding transmit time slot on DX is set in H.I.
Command Enable register (COMEN)
Addr=21h; Reset Value=80h
The En bits enable a command on one or more channels. All enabled channels will receive the entered data. At
least one channel must be enabled before every command.
E0..3=0: commands disabled on the corresponding channel 0..3
E0..3=1: commands enabled on the corresponding channel 0..3
PDR = 0: RAM is enabled also in Power Down.
PDR = 1: RAM is disabled in Power Down. In this way it’s possible to reduce the power consumption in Power
Down.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
POR
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
0
0
0
0
RES
LIN
AMU
STA
PD3
PD2
PD1
PD0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
0
0
0
1
PDR
0
0
0
E
3
E
2
E
1
E
0
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參數(shù)描述 |
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