參數(shù)資料
型號(hào)： STLC5048
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述： 完全可編程四通道解碼器和過濾器
文件頁(yè)數(shù)： 26/45頁(yè)
文件大?。?/td> 371K
代理商： STLC5048
STLC5048
26/45
EN2=0: Disable reception of selected time slot.
EN2=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO2 output.
R26..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred
to VFRO2 output.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most
significant bits in the programmed time slot, the 8 least significant bits in the following timeslot.
Example: if R26..R20=00:
Receive Time Slot ch #3 (DRTS3)
Addr=59h; Reset Value=00h
EN3=0: Disable reception of selected time slot.
EN3=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO3 output.
R36..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred
to VFRO3 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as
follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following
timeslot.
Example: if R36..R30=00:
PCMW Data Register (PCMWD)
Addr=5Ah; Reset Value=00h
Addr=5Bh; Reset Value=00h
This register is used to write receive PCM data via the MCU interface. Writing this register the IPCM interrupt
(if generated only by writing access) is automatically cleared.
In A/
μ
law only the first 8 bit are used. In linear code option both registers must be used.
TS0
TS1
15
14
13
12
11
10
9
8
6
5
4
3
7
2
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
0
1
EN3
R36
R35
R34
R33
R32
R31
R30
TS0
TS1
15
14
13
12
11
10
9
8
6
5
4
3
7
2
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
1
1
D15
D14
D13
D12
D11
D10
D9
D8
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