參數(shù)資料
型號: STLC5048
廠商: 意法半導體
元件分類: Codec
英文描述: FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
中文描述: 完全可編程四通道解碼器和過濾器
文件頁數(shù): 27/45頁
文件大?。?/td> 371K
代理商: STLC5048
27/45
STLC5048
PCMR Data Register (PCMRD)
Addr=5Ch; Reset Value=00h
Addr=5Dh; Reset Value=00h
Read only
This register is used to read transmit PCM data via the MCU interface. Reading this register the IPCM interrupt
(if generated only by reading access) is automatically cleared.
In A/
μ
law only the first 8 bit are used. In linear code option both registers must be read, first the LSB and after
the MSB.
PCM Control Register (PCMCTRL)
Addr= 5Eh; Reset Value=00h
Read only
PMW = 1: Data is not written every FS while writing PCM access data is enabled.
POW = 1: Data is not read every FS while reading PCM access data is enabled.
WRD = 1: Device is waiting for PCM data insertion in PCMWD register. The bit is reset after writing at least one byte.
RRD = 1: Data are available on PCMRD register. The bit is reset after reading the two bytes of the register (first
the LSB and after the MSB).
Tone Generation register (TONEG)
Addr=60h; Reset Value=00h
Tn
0
=0,Tn
1
=0: No tone is generated on ch #n
Tn
0
=1,Tn
1
=0: A tone with 25Hz frequency is generated on ch #n.
Tn
0
=0,Tn
1
=1: A tone with 1KHz frequency is generated on ch #n.
Tn
0
=1,Tn
1
=1: A tone with 3KHz frequency is generated on ch #n.
This register allows the generation of a tone in the RX direction.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
1
1
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
1
1
0
1
D15
D14
D133
D12
D11
D10
D9
D8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
1
1
1
0
RRD
WRD
POW
PMW
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
1
0
0
0
0
0
T3
1
T3
0
T2
1
T2
0
T1
1
T1
0
T0
1
T0
0
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