參數(shù)資料
型號: STLC1511
廠商: 意法半導(dǎo)體
英文描述: NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit
中文描述: NorthenLite⑩G.lite的BiCMOS模擬前端電路
文件頁數(shù): 5/31頁
文件大小: 358K
代理商: STLC1511
5/31
STLC1511
Figure 2. The block diagram of the STLC1511
3.2 Receive Path Specifications
Note: The first stage of the RxPGA provides a coarse gain of 0/20dB with a differential input or 6/26dB with a
single ended input. The second stage implements a programmable gain from 0dB to 20dB in 0.5dB steps.
12
14
D
S
Bandgap/
Bias Gen
14-bit
DAC
12-bit
ADC
4.416M
4.416M
35.328M/
5
8/4
69
2.56M/35.328M
2.56M
FREF
(External Clock Mode)
VCAP
OSCNB
DIGCLK
ENB
DRX
RXINN
RXINP
R
R
R
R
TXSIN[1:0]
FRM CLK
RXSOUT[1:0]
CK35M
V
I
0
5
TXOP
TXON
2
2
R
Exenl
Reonao
G
OSCNE
OSCPE
OSCPB
d
I
DTX
90
°
DIGREF
RXOPINP
RXOPINN
+
-
2/3/4/8
PFD
CP
+
-
G=1
fp=2MHz
fp=2MHz
A
A
A
T
0
0
0
0
0
0
+
-
+
-
+
-
Shaded blocks are only usabe when the PLL is active. Crystal based external resonator for the CPE Mode, LC
based resonator for the CO Oscillator Mode. 35.328 MHz external reference in CO External Clock Mode.
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