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參數(shù)資料
| 型號： | STLC1511 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
| 中文描述： | NorthenLite⑩G.lite的BiCMOS模擬前端電路 |
| 文件頁數(shù)： | 19/31頁 |
| 文件大?。?/td> | 358K |
| 代理商： | STLC1511 |
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19/31
STLC1511
Figure 9. Serial Interface Block Diagram
3.6.1 ADC Clip Indicator
Normally, the receive signal level is set such that the
input to the STLC1511 plus the RxPGA gain will not
saturate the input to the ADC converter (for maxi-
mum ADC input levels).
If the input signal is too large however and causes the
ADC to clip, the STLC1511 will report to the digital
chip that a clip has occurred. This is accomplished by
forcing the output data stream supplied to the digital
chip to either “7FFF” hex for an out of range positive
input or to “8000” hex for an out of range negative in-
put. This is highlighted in Figure 10.
TXSIN[1:0]
FRMCLK
RXSOUT[1:0]
CK35M
SDATA
SOUT
D
Q
14
8-bit Shift Register (x2)
14
to DAC parallel input
(Note: DAC input is
sampled on posedge
CKDAC)
CKDAC
(4.416MHz Clock from PLL)
SDATA
LD
SOUT
8-bit Shift Register (x2)
2
D
Q
12
12
from ADC parallel output
(Note: ADC output changes
on posedge of CKADC)
OUT[15:0]
DATA[15:0]
CK
CK
D
Q
CK35M
FRMCLK
TXSIN[0]
TXSIN[1]
msb
a5
a12
a4
a11
a3
a10
a2
a9
a1
a8
lsb
(x14)
(x12)
msb
b10
b3
b9
b2
b8
b1
b7
RXSOUT[0]
RXSOUT[1]
LD
D
Q
lsb
Data[15:0]
Out[15:0]
2
D
Q
D
Q
CKADC
(4.416MHz Clock from PLL)
D
Q
(x2)
2
(4 Dff to align data
edges as required)
D
Q
D
Q
D
Q
D
Q
a7
a6
b6
b5
b4
CKDAC
CKADC
Data clocked out by
ADC on this edge
Data sampled by
DAC on this edge
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| STLC2410B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:BLUETOOTH BASEBAND |
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