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參數(shù)資料
| 型號： | STLC1511 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
| 中文描述： | NorthenLite⑩G.lite的BiCMOS模擬前端電路 |
| 文件頁數(shù)： | 12/31頁 |
| 文件大?。?/td> | 358K |
| 代理商： | STLC1511 |
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STLC1511
12/31
3.4 Phase Lock Loop
The STLC1511 has been intended for use in either
the Central Office application (CO) using an external
clock of 35.328MHz, in the Central Office application
using an external 2.56Mhz clock and on-ship PLL , or
in a Customer Premise Equipment application (CPE).
In the CO application (External Clock Mode), the ref-
erence clock used for the converters and internally in
the STLC1511 is provided by an external reference.
In the CO application (Oscillator Mode), the
STLC1511 provides the ability to drive a LC oscillator
and generate the require clocks using an on-chip
PLL. In the Customer Premise Equipment (CPE) ap-
plication, the STLC1511 provides the crystal driver
for use with a external crystal and feedback network.
In the CPE application the tuning signal must be pro-
vided by the digital modem ASIC (STLC1510).
While the above descriptions highlight the intended
applications, the STLC1511 also has the flexibility to
provide a PLL function when used with a different ref-
erence frequency and external 35.328MHz crystal.
Table 4 highlights the different PLL modes for the
STLC1511.
3.4.1 Central Office (External Clock Mode)
In CO External Clock Mode the 35.328MHz refer-
ence clock on pin
FREF
is divided down and used in
both the TX and RX converters. In this mode of oper-
ation, the PLL and oscillator driver are powered
down.
External Clock Mode is selected by setting b5:b0 of
register “AFE Control 4” to “000000”. See section 3.7
for more information.
3.4.2 Central Office (Oscillator Mode)
In Oscillator Mode the 2.56MHz reference clock on
pin
FREF
is used as the reference clock for the
STLC1511 PLL. This clock is used to lock the LC os-
cillator frequency to 88.32MHz which is further divid-
ed down to provide the sampling clocks to both the
TX and RX converters and passed to the digital ASIC
STLC1510 as its PLL reference on the pin
DIGREF
.
The clock supplied to the digital ASIC STLC1510 via
DIGREF
is running at a rate of 17.664MHz in this
mode.
details the CO PLL and oscillator performance when
connected as shown in Figure 3, "CO Frequency vs.
Tuning Voltage".
CO Oscillator mode is selected by setting b5:b0 in
register “AFE Control 5” to “001001”. See section
"Digital Interface And Memory Map" on page 20 for
more information.
Table 4. PLL Application Modes
1
Description
FREF
freq
MHz
DIGREF
freq
MHz
PLL
active
LC Osc
freq
MHz
XTAL
freq
MHz
AFE Control 5
[b5:b0]
CO External Clock Mode
2
35.328
35.328
No
N/A
N/A
000000
CO Oscillator Mode
2.56
17.664
Yes
88.32
N/A
001001
CPE Mode
N/A
35.328
No
N/A
35.328
000110
PLL Misc. 1
1.536
35.328
Yes
N/A
35.328
011110
PLL Misc. 2
2.048
35.328
Yes
N/A
35.328
101110
PLL Misc. 3
4.096
35.328
Yes
N/A
35.328
111110
<1>Presently only applications described in this table are supported.
<2>The clock jitter specification for an externally supplied DAC or ADC clock (on pins FREF when in CO External Clock mode) is the
same as the jitter specification for the PLL.
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