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參數(shù)資料
| 型號： | STLC1511 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
| 中文描述： | NorthenLite⑩G.lite的BiCMOS模擬前端電路 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 358K |
| 代理商： | STLC1511 |
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STLC1511
Rx Opamp Power
Down
b3
0
1
Power up RxPGA
Power down RxPGA
1
not used
b7-b4
0
<1>During power down the Tx serial interface is also disabled and TXSCLK is tristated.
<2>During power down the Rx serial interface is also disabled and RXSCLK and RXSOUT[1:0] are tristated
Table 12. Detailed Register Map: AFE Control 4
Title:
AFE Control 4 (Misc. Control)
Label:
Misc Control
Access Type:
R/W
Address:
011
Bits Used:
5
Description:
Mode Control/Misc.
Bit Label
Bit(s)
Value
Bit Description
Reset
Clip Indicator Enable
b0
0
1
Clip indicator disabled
Clip indicator enabled
1
Tx Loop back
b1
0
1
Normal operation
Test mode. Tx data sent to serial I/F is
muxed to Rx input and trasmitted via the
serial I/F
0
PLL Phase/Freq Input
Select (Test Mode)
b2
0
1
Source of PLL phase-frequency detector
feedback input.
Output of feedback dividers.
Signal on FREF is sent directly to PFD (ref
input) and signal on
pin CK35M
is sent
directly to PFD (vco input).
0
DIV Output
(Test Mode only)
b3-b4
00
01
10
11
normal operation
Output of DIV69 counter is output to
DIGREF pin
Output of DIV2/3/4/8 counter is output to
DIGREF pin
Output of DIV5 counter is output to
DIGREF pin
0
not used
b7-b5
000
Table 11. Detailed Register Map: AFE Control 3
Title:
AFE Control 3 (Power Down Reg)
Label:
Power Down
Access Type:
R/W
Address:
010
Bits Used:
3
Description:
Power Down Register
Bit Label
Bit(s)
Value
Bit Description
Reset
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