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參數(shù)資料
| 型號： | STLC1511 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
| 中文描述： | NorthenLite⑩G.lite的BiCMOS模擬前端電路 |
| 文件頁數(shù)： | 21/31頁 |
| 文件大?。?/td> | 358K |
| 代理商： | STLC1511 |
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STLC1511
During a transaction, the first bit sent to the AFE de-
termines the type of transaction, R/W=”1” corre-
sponds to a read transaction while R/W=”0”
corresponds to a write transaction. The next three
bits, address[a2:a0], determine which of the 8 AFE
registers will be accessed (Table 8). This is followed
by the 8-bit data word.
In both Read and Write transactions, bit 0 (
LSB
) of
the serially transferred 8-bit word is clocked from the
data source first (the data source being the external
DSP during Write transactions; the STLC1511 during
Read transactions).
The definition of these fields within the 8-bit word is
outlined below in Table 8 and in the detailed register
maps following.
When the voltage on the
RESETN
pin is low, the bits
in the control register will be reset as per defined in
the detailed register maps.
For a write operation, the data on the
DRX
pin is
latched into the STLC1511 on the negative edge of
the
DIGCLK
signal. The data should change state on
the positive edge of the clock.
For a read operation, the data on the
DTX
pin is out-
put on the positive edge of the clock on pin
DIGCLK
.
Table 8. AFE Register Map Summary
Addr
[a2:a0]
Name
D7
D6
D5
D4
D3
D2
D1
D0
Type
000
STLC1511 Control 1 (Rx
PGA Gain)
Rx PGA Gain
RW
001
STLC1511 Control 2 (Tx
PGA Gain)
not used
Tx PGA Gain
RW
010
STLC1511 Control 3
(Power Down Reg)
not used
Rx
Opa
mp
Pow
er
Dow
n
not
use
d
Rx
Pow
er
Dow
n
Tx
Pow
er
Dow
n
RW
011
STLC1511 Control 4
(Misc. Control)
not
use
d
DIV Output
(Test mode)
PLL
PFD
inpu
t sel
Tx
Loo
p
back
Clip
Indic
ator
ena
ble
RW
100
AFE Control 5
(PLL Control)
not
use
d
DIG-
REF
Ena
ble
FREF Mode
PLL
Mod
e
Osc
Mod
e
1
Clock Source
Control
R/W
101
not used
not used
110
not used
not used
111
AFE Status
not used
Clip
Stat
us
R
<1>Presently there is no difference in the oscillator driver between Oscillator Mode and CPE modes so this bit is unused. However,
it may be required in the future and should be programmed correctly in case needed.
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