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| 型號： | STLC1511 |
| 廠商： | 意法半導體 |
| 英文描述： | NorthenLite⑩ G.lite BiCMOS Analog Front-End Circuit |
| 中文描述： | NorthenLite⑩G.lite的BiCMOS模擬前端電路 |
| 文件頁數(shù)： | 24/31頁 |
| 文件大?。?/td> | 358K |
| 代理商： | STLC1511 |
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STLC1511
24/31
Table 13. Detailed Register Map: AFE Control 5
Title:
AFE Control 5 (PLL Control)
Label:
PLL Control
Access Type:
R/W
Address:
100
Bits Used:
7
Description:
PLL Control Register
Bit Label
Bit(s)
Value
Bit Description
Reset
Clock Source Control
b0-b1
00
01
10
11
(CO External Clock Mode.) Output of
clock selection MUX is from
FREF
pin.
This state also powers down the PLL and
oscillator driver.
(CO Oscillator Mode.) Output of clock
selection MUX is from output of divide by
5.
(CPE Mode). Output of clock selection
MUX is from output of oscillator driver.
(Other CPE Mode). Output of clock
selection MUX is from output of oscillator
driver.
00
OSC Mode
1
b2
0
1
(CO Oscillator mode.) AFE is configured
to drive external 88.32MHz LC oscillator.
(CPE mode.) AFE is configured to drive
external 35.328MHz crystal oscillator.
1
PLL Mode
b3
0
1
PLL active (PFD,CP active)
PLL Inactive (PFD,CP powered down)
0
FREF Mode
2
b5-b4
00
01
10
11
FREF frequency is 2.56MHz
FREF frequency is 1.536MHz
FREF frequency is 2.048MHz
FREF frequency is 4.096MHz
00
DIGREF Enable
b6
0
1
DIGREF
Output pin tristated
DIGREF
Output pin active
1
reserved
b7
0
<1>Presently there is no difference in the oscillator driver between CO Oscillator and CPE modes so this bit is unused. However, it
may be required in the future and should be programmed correctly in case needed.
<2>For FREF at 2.56MHz (b5:b4 = “00”), the compare frequency for the PLL is at 1.28MHz. For all other FREF modes the compare
frequency is at 512kHz.
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