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參數(shù)資料
| 型號： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 95/172頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
29
The EBI supports byte, word, and long-word transfers. Ports are accessed through the use of asyn-
chronous cycles controlled by the data transfer size (SIZ1 and SIZ0) and the data size acknowledge
pin (DSACK1).
Port width is the maximum number of bits accepted or provided during a bus transfer. External de-
vices must follow the handshake protocol described below. Control signals indicate the beginning
of the cycle, the address space, the size of the transfer, and the type of cycle. The selected device
controls the length of the cycle. Strobe signals, one for the address bus and another for the data
bus, indicate the validity of an address and provide timing information for data. The EBI operates in
an asynchronous mode for any port width.
To add flexibility and minimize the necessity for external logic, MCU chip select logic can be syn-
chronized with EBI transfers. Chip select logic can also provide internally-generated bus control sig-
nals for these accesses. Refer to 3.9 Chip Selects for more information.
3.6 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs.
At the beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code
signals. The size signals indicate the number of bytes remaining to be transferred during an oper-
and cycle. They are valid while the address strobe (AS) is asserted. Table 17 shows SIZ0 and SIZ1
encoding. The read/write (R/W) signal determines the direction of the transfer during a bus cycle.
This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is
asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The
signal can remain low for two consecutive write cycles.
3.6.1 Function Codes
Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can
be considered address extensions that automatically select one of eight address spaces to which
an address applies. These spaces are designated as either user or supervisor, and program or data
spaces. Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spac-
es 0 to 3 are not used. Address space 7 is designated CPU space. CPU space is used for control
information not normally associated with read or write bus cycles. Function codes are valid while
AS is asserted.
Table 18 displays CPU16 address space encodings.
Table 17 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
0
1
Byte
1
0
Word
1
Three Byte
0
Long Word
Table 18 CPU16 Address Space Encoding
FC2
FC1
FC0
Address Space
1
0
Reserved
1
0
1
Supervisor Data Space
1
0
Supervisor Program Space
1
CPU Space
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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