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| 型號(hào)： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 13/172頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
11
2.5 MCU Signal Function
Table 6 MCU Signal Function
Signal Name
Mnemonic
Function
Address Bus
ADDR[19:0]
20-bit address bus used by CPU16
ADC Analog Input
AN[5:0]
Inputs to ADC multiplexer
Address Strobe
AS
Indicates that a valid address is on the address bus
Bus Grant
BG
Indicates that the MCU has relinquished the bus
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership
Bus Error
BERR
Indicates that a bus error has occurred
Breakpoint
BKPT
Signals a hardware breakpoint to the CPU
Bus Request
BR
Indicates that an external device requires bus mastership
System Clockout
CLKOUT
System clock output
Emulation Mode
Chip-Selects
CSE, CSM
CSE selects external emulation devices at internally-mapped ad-
dresses. It is used to emulate I/O ports. CSM has no function on the
MC68HC916X1. It is driven high if the SCIM is configured for emu-
lation mode.
Chip-Selects
CS10, CS[6:5],
CS3, CS0
Select external devices at programmed addresses
Data Bus
DATA[15:0]
16-bit data bus
Data Strobe
DS
During a read cycle, indicates that an external device should place
valid data on the data bus. During a write cycle, indicates that valid
data is on the data bus.
Data and Size
Acknowledge
DSACK1
Asserted by external devices during asynchronous transfers to in-
dicate receipt of data and width of receiving port
Development Serial In,
Out, Clock
DSI, DSO, DSCLK Serial I/O and clock for background debug mode
External Clock
ECLK
M6800 bus clock output
Crystal Oscillator
EXTAL, XTAL
Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
Function Codes
FC[2:0]
Identify processor state and current address space
Freeze
FREEZE
Indicates that the CPU16 has entered background mode
Instruction Pipeline
IPIPE[1:0]
Indicates instruction pipeline activity
Interrupt Request
IRQ[7:6]
Request interrupt service from the CPU16
Master In Slave Out
MISO
Serial input to SPI in master mode; serial output from SPI in slave
mode
Clock Mode Select
MODCLK
Selects the source and type of system clock
Master Out Slave In
MOSI
Serial output from SPI in master mode; serial input to SPI in slave
mode
Peripheral Chip-Selects
PCS[3:0]
QSPI peripheral chip selects
Port A
PA[7:0]
Port A digital input or output signals
Port B
PB[7:0]
Port B digital input or output signals
Port C
PC[3:0]
Port C digital input/output port signals
Port E
PE1, PE[7:4]
Port E digital I/O port signals
Port F
PF0, PF[7:6]
Port F digital I/O port signals
Port G
PG[7:0]
Port G digital I/O signals
Port GP
PGP[7:0]
GPT digital I/O port signal
Port H
PH[7:0]
Port H digital I/O signal
Port QS
PQS[7:0]
QSM digital I/O port signal
Pulse Accumulator Input
PAI
Input to the GPT pulse accumulator
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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