參數(shù)資料
型號： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 68/172頁
文件大小： 1200K
代理商： SPMC916X1CTH16
MOTOROLA
MC68HC916X1
16
MC68HC916X1TS/D
The module configuration register controls system configuration. It can be read or written at any
time, except for the module mapping (MM) bit, which must remain set to one and can only be written
once.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Watchdog Enable
0 = When FREEZE is asserted, the software watchdog continues to run.
1 = When FREEZE is asserted, the software watchdog is disabled.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
CPUD — CPU Development Support Disable
0 = Instruction pipeline signals available on pins IPIPE0 and IPIPE1
1 = Pins IPIPE0 and IPIPE1 placed in high-impedance state unless a breakpoint occurs
CPUD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode.
SHEN[1:0] — Show Cycle Enable
This field determines how the external bus is driven during internal transfer operations. A show cycle
allows internal transfers to be monitored externally. Table 8 shows whether show cycle data is driven
externally, and whether external bus arbitration can occur. To prevent bus conflict, external peripherals
must not be enabled during show cycles.
SUPV — Supervisor/Unrestricted Data Space
This bit has no effect because the CPU16 always operates in the supervisor mode.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
The logic state of MM determines the value of ADDR23 for IMB module addresses. Because AD-
DR[23:20] are driven to the same state as ADDR19, MM must be set to one. If MM is cleared, IMB mod-
ules are inaccessible. This bit can be written only once after reset.
ABD — Address Bus Disable
0 = Pins ADDR[2:0] operate normally.
1 = Pins ADDR[2:0] are disabled.
ABD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode. ABD
can be written only once after reset.
Table 8 Show Cycle Enable Field
SHEN
Action
00
Show cycles disabled, external arbitration enabled
01
Show cycles enabled, external arbitration disabled
10
Show cycles enabled, external arbitration enabled
11
Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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