參數(shù)資料
型號(hào)： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 34/172頁
文件大?。?/td> 1200K
代理商： SPMC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
129
9.6.2 Bootstrap Operation
After reset, the CPU begins bootstrap operation by fetching initial values for its internal registers
from special bootstrap word addresses $000000 through $000006. If BOOT = 0 and STOP = 0 in
FEExMCR, the flash EEPROM module is configured to recognize these addresses after a reset and
provide this information from the FEExBS[3:0] bootstrap registers in the flash EEPROM control
block. The information in these registers is programmed by the user.
9.6.3 Normal Operation
The flash EEPROM module allows a byte or aligned-word read in one bus cycle. Long-word reads
require two bus cycles.
The module checks function codes to verify access privileges. All control block addresses must be
in supervisor data space. Array accesses are defined by the state of ASPC[1:0] in FEExMCR. Ac-
cess time is governed by the WAIT[1:0] field in FEExMCR.
Accesses to any address in the address block defined by FEExBAH and FEExBAL which does not
fall within the array are ignored, allowing external devices to adjoin flash EEPROM arrays which do
not entirely fill the entire address space specified by FEExBAH and FEExBAL.
9.6.4 Program/Erase Operation
An erased flash bit has a logic state of one. A bit must be programmed to change its state from one
to zero. Erasing a bit returns it to a logic state of one. Programming and erasing the flash module
requires a series of control register writes and a write to an array address. The same procedure is
used to program control registers that contain flash shadow bits. Programming is restricted to a sin-
gle byte or aligned word at a time. The entire array and the shadow register bits are erased at the
same time.
When multiple flash modules share a single VFPE pin, do not program or erase more than one flash
module at a time. Normal accesses to modules that are not being programmed are not affected by
programming or erasure of another flash module.
The following paragraphs give step-by-step procedures for programming and erasure of flash EE-
PROM arrays. Refer to 11 Electrical Characteristics for information on programming and erasing
specifications for the flash EEPROM module.
9.6.4.1 Programming
The following steps are used to program a flash EEPROM array. Figure 22 is a flowchart of the
programming operation. Refer to Figures 45 and 46 in 11 Electrical Characteristics for VFPE to
VDD relationships during programming.
1.
Increase voltage applied to the VFPE pin to program/erase/verify level.
2.
Clear the ERAS bit and set the LAT bit in FEExCTL. This enables the programming address
and data latches.
3.
Write data to the address to be programmed. This latches the address to be programmed
and the programming data.
4.
Set the ENPE bit in FEExCTL. This starts the program pulse.
5.
Delay the proper amount of time for one programming pulse to take place. Delay is speci-
fied by parameter pwpp.
6.
Clear the ENPE bit in FEExCTL. This stops the program pulse.
7.
Delay while high voltage to array is turned off. Delay is specified by parameter tpr.
8.
Read the address to verify that it has been programmed.
9.
If the location is not programmed, repeat steps 4 through 7 until the location is pro-
grammed, or until the specified maximum number of program pulses has been reached.
Maximum number of pulses is specified by parameter npp.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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