參數(shù)資料
型號(hào)： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 122/172頁
文件大小： 1200K
代理商： SPMC916X1CTH16
MOTOROLA
MC68HC916X1
53
MC68HC916X1TS/D
4.3.1 Condition Code Register
S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed
1 = Perform NOP when LPSTOP instruction is executed
MV — Accumulator M overflow flag
MV is set when an overflow into AM35 has occurred.
H — Half Carry Flag
H is set when a carry from A3 or B3 occurs during BCD addition.
EV — Extension Bit Overflow Flag
EV is set when an overflow into AM31 has occurred.
N — Negative Flag
N is set when the MSB of a result register is set.
Z — Zero Flag
Z is set when all bits of a result register are zero.
V — Overflow Flag
V is set when a two’s complement overflow occurs as the result of an operation.
C — Carry Flag
C is set when a carry or borrow occurs during an arithmetic operation. This flag is also used during shift
and rotate to facilitate multiple word operations.
IP[2:0] — Interrupt Priority Field
The priority value in this field (0 to 7) is used to mask interrupts.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from AM using TMER or TMET is given maximum
positive or negative value, depending on the state of the AM sign bit before overflow.
PK[3:0] — Program Counter Address Extension Field
This field is concatenated with the program counter to form a 20-bit address.
4.4 Data Types
The CPU16 supports the following data types:
Bit data
8-bit (byte) and 16-bit (word) integers
32-bit long integers
16-bit and 32-bit signed fractions (MAC operations only)
20-bit effective address consisting of 16-bit page address plus 4-bit extension
A byte is eight bits wide and can be accessed at any byte location. A word is composed of two con-
secutive bytes, and is addressed at the lower byte. Instruction fetches are always accessed on word
boundaries. Word operands are normally accessed on word boundaries as well, but can be access-
ed on odd byte boundaries, with a substantial performance penalty.
To be compatible with the M68HC11, misaligned word transfers and misaligned stack accesses are
allowed. Transferring a misaligned word requires two successive byte operations.
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S
MV
H
EV
N
Z
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IP[2:0]
SM
PK[3:0]
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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