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參數(shù)資料
| 型號(hào)： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 89/172頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
23
The synthesizer locks when the VCO frequency is equal to fref. Lock time is affected by the filter
time constant and by the amount of difference between the two comparator inputs. Whenever a
comparator input changes, the synthesizer must relock. Lock status is shown by the SLOCK bit in
SYNCR. During power-up, the MCU does not come out of reset until the synthesizer locks. Crystal
type, characteristic frequency, and layout of external oscillator circuitry affect lock time.
When the clock synthesizer is used, SYNCR determines operating frequency and certain operating
parameters. The W and Y[5:0] bits are located in the PLL feedback path, enabling frequency mul-
tiplication by a factor of up to 256. When the W or Y values change, VCO frequency changes, and
there is a VCO relock delay. The SYNCR X bit controls a divide-by circuit that is not in the synthe-
sizer feedback loop. When X = 0 (reset state), a divide-by-four circuit is enabled, and the system
clock frequency is one-fourth the VCO frequency (fVCO). When X = 1, a divide-by-two circuit is en-
abled, and system clock frequency is one-half the VCO frequency (fVCO). There is no relock delay
when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
The reset state of SYNCR ($3F00) results in a power-on fsys of 16.78 MHz when the fref is 4.194
MHz.
For the device to perform correctly, the clock and frequency selected by the W, X, and Y bits must
be within the limits specified for the MCU.
Internal VCO frequency is determined by the following equations:
or
3.3.3 Clock Control
The clock control circuits determine system clock frequency and clock operation under special cir-
cumstances, such as loss of synthesizer reference or low-power mode. Clock source is determined
by the logic state of the MODCLK pin during reset.
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the
upper byte of SYNCR. Bits in the lower byte show the status of, or control the operation of, internal
and external clocks. Because the CPU16 always operates in supervisor mode, SYNCR can be read
or written at any time.
1. Ensure that initialization software does not change the value of this bit. It should always be zero.
SYNCR — Clock Synthesizer Control Register
$YFFA04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
X
Y[5:0]
EDIV
0
RESET:
0
1
0
U
0
f
sys
f
ref
128
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1
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X
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VCO
4f
sys
if X = 0
=
f
VCO
2f
sys
if X = 1
=
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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