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參數(shù)資料
| 型號(hào)： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 102/172頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
35
Interrupt recognition is based on the states of interrupt request signals IRQ7 and the IP mask value.
Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has
the highest priority.
NOTE
On the MC68HC916X1, the only external interrupts available are IRQ6 and IRQ7.
The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority
masks. Masks prevent an interrupt request of a priority less than or equal to the mask value (except
for IRQ7) from being recognized and processed. When IP contains %000, no interrupt is masked.
During exception processing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Re-
quest lines are connected internally by a wired-NOR. Simultaneous requests with different priorities
can be made. Internal assertion of an interrupt request signal does not affect the logic state of the
corresponding MCU pin.
External interrupt requests are routed to the CPU16 through the external bus interface and SCIM
interrupt control logic. The CPU treats external interrupt requests as though they had come from
the SCIM.
External IRQ6 is an active-low level-sensitive input. External IRQ7 is an active-low transition-sen-
sitive input. It requires both an edge and a voltage level for validity.
IRQ6 is maskable. IRQ7 is non-maskable. The IRQ7 input is transition-sensitive to prevent redun-
dant servicing and stack overflow. A non-maskable interrupt is generated each time IRQ7 is assert-
ed, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request
input circuitry has hysteresis. To be valid, a request signal must be asserted for at least two con-
secutive clock periods. Valid requests do not cause immediate exception processing, but are left
pending. Pending requests are processed at instruction boundaries or when exception processing
of higher-priority exceptions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request
is serviced. If an interrupt request of equal or lower priority than the current IP mask value is made,
the CPU does not recognize the occurrence of the request in any way.
3.8.1 Interrupt Acknowledge and Arbitration
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16
detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it
performs a CPU space read from address $FFFFF: [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the
highest priority interrupt request on the address bus, and it acquires an exception vector number
from the interrupt source. The mask value also serves two purposes: it is latched into the CCR IP
field to mask lower-priority interrupts during exception processing, and it is decoded by modules
that have requested interrupt service to determine whether the current interrupt acknowledge cycle
pertains to them.
Modules that have requested interrupt service decode the IP value placed on the address bus at
the beginning of the interrupt acknowledge cycle. If their requests are at the specified IP level, they
respond to the cycle. Arbitration between simultaneous requests of the same priority is performed
by serial contention between module interrupt arbitration (IARB) field bit values.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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