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參數(shù)資料
| 型號(hào)： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 113/172頁(yè) |
| 文件大小： | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
45
3.10 General-Purpose Input/Output
The SCIM contains six general-purpose input/output ports: ports A, B, E, F, G, and H. (Port C, an
output-only port, is included under the discussion of chip selects). Ports A, B, and G are available
in single-chip mode only and port H is available in single-chip or 8-bit expanded modes only. Ports
E, F, G, and H have an associated data direction register to configure each pin as input or output.
Ports A and B share a data direction register that configures each port as input or output. Ports E
and F have associated pin assignment registers that configure each pin as digital I/O or an alternate
function. Port F has an edge-detect flag register that indicates whether a transition has occurred on
any of its pins.
Table 31 shows the shared functions of the general-purpose I/O ports and the modes in which they
are available.
Access to the port A, B, E, F, G, and H data and data direction registers, and the port C, E, and F
pin assignment registers require three clock cycles to ensure timing compatibility with external port
replacement logic. Port registers are byte-addressable and are grouped to allow coherent word ac-
cess to port data register pairs A-B and G-H, as well as word-aligned long word coherency of A-B-
G-H port data registers.
If emulation mode is enabled, the emulation mode chip-select signal CSE is asserted whenever an
access to ports A, B, E, G, and H data and data direction registers or the port E pin assignment
register is made. The SCIM does not respond to these accesses, but allows external logic, such as
a Motorola port replacement unit (PRU) MC68HC33 to respond. Port C data and data direction reg-
ister, port F data and data direction register, and the port F pin assignment register remain acces-
sible.
A write to the port A, B, E, F, G, or H data register is stored in the internal data latch. If any port pin
is configured as an output, the value stored for that bit is driven on the pin. A read of the port data
register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the
value read is the value stored in the register.
Table 31 General-Purpose I/O Ports
Port
Shared Function
Modes
A
ADDR[18:11]
Single Chip
B
ADDR[10:3]
Single Chip
E
Bus Control
All
F
IRQ[7:6]/MODCLK
All
G
DATA[15:8]
Single Chip
H
DATA[7:0]
Single Chip, 8-Bit Expanded
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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