參數(shù)資料
型號: SPC5121YVY400BR
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數(shù): 71/86頁
文件大?。?/td> 719K
代理商: SPC5121YVY400BR
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 3
Freescale Semiconductor
73
3.3.23
IEEE 1149.1 (JTAG)
Figure 52. Timing Diagram – JTAG Clock Input
Table 50. JTAG Timing Specification
Sym
Characteristic
Min
Max
Unit
SpecID
TCK frequency of operation
0
25
MHz
A23.1
1
TCK cycle time
40
ns
A23.2
2
TCK clock pulse width measured at 1.5V
1.08
ns
A23.3
3
TCK rise and fall times
0
3
ns
A23.4
4TRST setup time to tck falling edge1
1 TRST is an asynchronous signal. The setup time is for test purposes only.
10
ns
A23.5
5TRST assert time
5
ns
A23.6
6
Input data setup time2
2 Non-test, other than TDI and TMS, signal input timing with respect to TCK.
5
ns
A23.7
7
Input data hold time2
15
ns
A23.8
8
TCK to output data valid3
3 Non-test, other than TDO, signal output timing with respect to TCK.
030
ns
A23.9
9
TCK to output high impedance3
0
30
ns
A23.10
10
TMS, TDI data setup time.
5
ns
A23.11
11
TMS, TDI data hold time.
1
ns
A23.12
12
TCK to TDO data valid.
0
15
ns
A23.13
13
TCK to TDO high impedance.
0
15
ns
A23.14
TCK
VM
3
22
1
VM = Midpoint Voltage
Numbers shown reference JTAG Timing Specification Table
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