參數(shù)資料
型號(hào)： SPC5121YVY400BR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁(yè)數(shù)： 60/86頁(yè)
文件大?。?/td> 719K
代理商： SPC5121YVY400BR
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 3
Freescale Semiconductor
63
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H
parameters are programmed via the HSYN_PARA register; And the PW_V, BP_V and FP_V parameters are programmed via
the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions on these parameters.
Figure 43 depicts the synchronous display interface timing for access level, and Table 38 lists the timing parameters.
Figure 43. LCD Interface Timing Diagram – Access Level
tFPH
HSYNC Front Porch Width
FP_H * tPCP
ns
A15.4
tSW
Screen Width
DELTA_X * tPCP
ns
A15.5
tHSP
HSYNC (Line) Period
(PW_H + BP_H + DELTA_X + FP_H) * tPCP
ns
A15.6
tPWV
VSYNC Pulse Width
PW_V * tHSP
ns
A15.7
tBPV
VSYNC Back Porch Width
BP_V * tHSP
ns
A15.8
tFPV
VSYNC Front Porch Width
FP_V * tHSP
ns
A15.9
tSH
Screen Height
DELTA_Y * tHSP
ns
A15.10
tVSP
VSYNC (Frame) Period
(PW_V + BP_V + DELTA_Y + FP_H) * tHSP
ns
A15.11
1
Display interface pixel clock period immediate value (in nanosecond).
Table 38. LCD Interface Timing Parameters – Access Level
Parameter
Description
Min
Typ
Max
Unit
SpecID
tCKH
LCD Interface Pixel Clock High Time
tPCP * 0.4
tPCP * 0.5
tPCP * 0.6
ns
A15.12
tCKL
LCD Interface Pixel Clock Low Time
tPCP * 0.4
tPCP * 0.5
tPCP * 0.6
ns
A15.13
tDSU
LCD Interface Data Setup Time
5.0
-
ns
A15.14
tDHD
LCD Interface Data Hold Time
6.0
-
ns
A15.15
tCSU
LCD Interface Control Signal Setup Time
5.0
-
ns
A15.16
tCHD
LCD Interface Control Signal Hold Time
6.0
-
ns
A15.17
Table 37. LCD Interface Timing Parameters – Pixel Level (continued)
Name
Description
Value
Unit
SpecID
tCKH
tCKL
tDHD
tDSU
tCSU
DIU_HSYNC
DIU_VSYNC
DIU_DE
DIU_CLK
DIU_LD[23:0]
tCHD
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