參數(shù)資料
型號(hào)： SPC5121YVY400BR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁(yè)數(shù)： 58/86頁(yè)
文件大?。?/td> 719K
代理商： SPC5121YVY400BR
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 3
Freescale Semiconductor
61
3.3.15
DIU
The DIU is a display controller designed to manage the TFT LCD display.
3.3.15.1
Interface to TFT LCD Panels, Functional Description
Figure 40 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with
positive polarity. The sequence of events for active matrix interface timing is:
DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode,
DIU_CLK runs continuously. This signal frequency could be from 5 to 100 MHz depending on the panel type.
DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse.
DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse.
DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.
When disabled, the data is invalid and the trace is off.
Figure 40. Interface Timing Diagram for TFT LCD Panels
3.3.15.2
Interface to TFT LCD Panels, Electrical Characteristics
Figure 41 depicts the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters
shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal (meaning
the data and sync. signals change at the rising edge of it) and active-high polarity of the DIU_HSYNC, DIU_VSYNC and
DIU_DE signal. You can select the polarity of the DIU_HSYNC and DIU_VSYNC signal via the SYN_POL register, whether
active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. And, pixel clock inversion and
a flexible programmable pixel clock delay is also supported, programed via the DIU Clock Config Register (DCCR) in the
system clock module.
DIU_LD[23:0]
DIU_CLK
DIU_DE
DIU_HSYNC
DIU_VSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
12
3
m-1
m
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