參數(shù)資料
型號(hào)： SPC5121YVY400BR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁(yè)數(shù)： 39/86頁(yè)
文件大?。?/td> 719K
代理商： SPC5121YVY400BR
MPC5121E/MPC5123 Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
44
T is the flash clock cycle.
T= 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)
T= 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)
3.3.9
PATA
The MPC5121e/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate
with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is
completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units
(nanoseconds).
ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data
setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the
ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and
ATA drive for different ATA protocols and their respective timing. See the MPC5121e/MPC5123 Reference Manual.
The MPC5121e/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE
strobe in PIO and Multiword DMA modes.
Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that
required by the ATA-4 specification.
Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that
required by the ATA-4 specification.
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.
This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate
with the drive.
tWP
NFC_WP Pulse Width
T-1
—
ns
A8.5
tALS
NFC_ALE Setup Time
T-1
—
ns
A8.6
tALH
NFC_ALE Hold Time
T-1
—
ns
A8.7
tDS
Data Setup Time
T-2
—
ns
A8.8
tDH
Data Hold Time
T-1
—
ns
A8.9
tWC
Write Cycle Time
2T
—
ns
A8.10
tWH
NFC_WE Hold Time
T-1
—
ns
A8.11
tRR
Ready to NFC_RE Low
5T+2
—
ns
A8.12
tRP
NFC_RE Pulse Width
1.5T-1
—
ns
A8.13
tRC
READ Cycle Time
2T
—
ns
A8.14
tREH
NFC_RE High Hold Time
0.5T
—
ns
A8.15
Table 24. NFC Timing Characteristics (continued)
Timing
parameter
Description
Min. value
Max. value
Unit
SpecID
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