參數(shù)資料
型號： SPC5121YVY400BR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數(shù)： 19/86頁
文件大?。?/td> 719K
代理商： SPC5121YVY400BR
MPC5121E/MPC5123 Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
26
3.2.4
e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
Sys PLL VCO frequency1
fVCOsys
400
—
800
MHz
O3.3
Sys PLL VCO output jitter (Dj),
peak to peak / cycle
fVCOjitterDj
—
40
ps
O3.4
Sys PLL VCO output jitter (Rj), rms
1 sigma
fVCOjitterRj
—
12
ps
O3.5
Sys PLL relock time - after power
up 3
tlock1
—
200
μsO3.6
Sys PLL relock time - when power
was on4
tlock2
—
170
μsO3.7
1 The SYS_XTALI frequency and PLL Configuration bits must be chosen such that the resulting system
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies.
2 This represents total input jitter - short term and long term combined. Two different types of jitter can exist
on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic
jitter is passed into and through the PLL to the internal clock circuitry.
3 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and
CORE_SYSCLK are reached during the power-on reset sequence.
4 PLL-relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled
and subsequently re-enabled during sleep modes.
Table 15. e300 PLL Specifications
Characteristic
Sym
Min
Typical
Max
Unit
SpecID
e300 frequency1
1 The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies,
CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies in Table 16. There is a hard coded relationship between fcore and fVCOcore (fcore =
fVCOcore/2).
fcore
200
—
400
MHz
O4.1
e300 PLL VCO frequency1
fVCOcore
400
—
800
MHz
O4.3
e300 PLL input clock frequency
fCSB_CLK
50
—
200
MHz
O4.4
e300 PLL input clock cycle time
tCSB_CLK
5
—
20
ns
O4.5
e300 PLL relock time2
2 PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and
CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep modes.
tlock
—
200
μsO4.6
Table 14. System PLL Specifications
Characteristic
Sym
Min
Typical
Max
Unit
SpecID
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SPC5123YVY300B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information
SPC5123YVY300BR 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Advance Information
SPC5123YVY400B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:e300 Power Architecture processor core
SPC5123YVY400BR 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:e300 Power Architecture processor core
SPC5125 制造商:ELECTROMAGNETIC CORPORATI 功能描述:_
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