參數(shù)資料
型號: SPC5121YVY400BR
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數(shù): 53/86頁
文件大小: 719K
代理商: SPC5121YVY400BR
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 3
Freescale Semiconductor
57
Figure 34. Ethernet Timing Diagram – MII Rx Signal
Figure 35. Ethernet Timing Diagra – MII Tx Signal
Figure 36. Ethernet Timing Diagram – MII Async
1 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.
Table 32. MII Tx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t5
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER
invalid
3
ns
A11.5
t6
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid
25
ns
A11.6
t7
TX_CLK pulse width high
35%
65%
TX_CLK Period1
1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 Specification.
A11.7
t8
TX_CLK pulse width low
35%
65%
TX_CLK Period1
A11.8
Table 33. MII Async Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t9
CRS, COL minimum pulse width
1.5
TX_CLK Period
A11.9
t4
t3
t1
t2
RX_CLK (Input)
RXD[3:0] (inputs)
RX_DV
RX_ER
t8
t7
t5
TX_CLK (Input)
TXD[3:0] (Outputs)
TX_EN
TX_ER
t6
t9
CRS, COL
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