參數資料
型號: SPC5121YVY400BR
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA516
封裝: 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, TFBGA-516
文件頁數: 54/86頁
文件大?。?/td> 719K
代理商: SPC5121YVY400BR
MPC5121E/MPC5123 Data Sheet, Rev. 3
Electrical and Thermal Characteristics
Freescale Semiconductor
58
Figure 37. Ethernet Timing Diagram – MII Serial Management
3.3.12
USB ULPI
This section specifies the USB ULPI timing.
For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004.
Table 34. MII Serial Management Channel Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t10
MDC falling edge to MDIO output delay
0
25
ns
A11.10
t11
MDIO (input) to MDC rising edge setup
10
ns
A11.11
t12
MDIO (input) to MDC rising edge hold
0
ns
A11.12
t13
MDC pulse width high1
1 MDC is generated by MPC5121e/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC
MII_SPEED control register is changed during operation. See the MPC5121e/MPC5123 Reference Manual.
160
ns
A11.13
t14
MDC pulse width low1
160
ns
A11.14
t15
MDC period2
2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5121e/MPC5123 Reference
Manual.
400
ns
A11.15
t14
t13
t12
MDC (Output)
MDIO (Input)
MDIO (Output)
t11
t10
t15
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