參數(shù)資料
型號(hào)： SP37E760-MC
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 外設(shè)及接口
英文描述： 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： QFP-100
文件頁數(shù)： 35/78頁
文件大?。?/td> 510K
代理商： SP37E760-MC
SMSC DS – SP37E760
Rev. 04/13/2001
5.4.4
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are
supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict
with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that
mode. The port registers vary depending on the mode field in the ecr (Table 19). Table 18 lists these dependencies.
Operation of the devices in modes other that those specified is undefined.
Table 18 - ECP Register Definitions
NAME
ADDRESS (Note 1)
data
+000h R/W
ecpAFifo
+000h R/W
dsr
+001h R/W
dcr
+002h R/W
cFifo
+400h R/W
ecpDFifo
+400h R/W
tFifo
+400h R/W
cnfgA
+400h R
cnfgB
+401h R/W
ecr
+402h R/W
Note 1:
These addresses are added to the parallel port base address as selected by configuration register or jumpers.
Note 2:
All addresses are qualified with AEN. Refer to the AEN pin definition.
Table 19 - Mode Descriptions
MODE
DESCRIPTION
(Refer to ECR Register Description)
000
SPP mode
001
PS/2 Parallel Port mode
010
Parallel Port Data FIFO mode
011
ECP Parallel Port mode
100
EPP mode (If this option is enabled in the configuration registers)
101
(Reserved)
110
Test mode
111
Configuration mode
5.4.4.1
DATA and ecpAFifo PORT
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the
nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation, PD0 - PD7 ports are read and output to the host CPU.
Mode 011 (ECP FIFO - Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the
ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the
forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing
Diagrams section of this data sheet .
5.4.4.2
DEVICE STATUS REGISTER (dsr)
ADDRESS OFFSET = 01H
REGISTER DEFINITIONS
ECP MODES
000-001
011
All
All
010
011
110
111
111
All
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
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