- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365670 > SP37E760-MC (STANDARD MICROSYSTEMS CORP) 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS PDF資料下載
參數(shù)資料
| 型號： | SP37E760-MC |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 15/78頁 |
| 文件大?。?/td> | 510K |
| 代理商： | SP37E760-MC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
SMSC DS – SP37E760
Page 15
Rev. 04/13/2001
4
The SP37E760 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE
registers and the NS16550A. The UARTs perform serial-to-parallel conversion on received characters and parallel-
to-serial conversion on transmit characters. The data rates are independently programmable from 115.2K baud down
to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity;
and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing
the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data
rate. Refer to the SP37E760 Configuration Registers for information on disabling, powering down and changing the
base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic
“1”. When OUT2 is a logic “0” the UART Interrupt is disabled.
SERIAL PORT (UART)
4.1 Register Description
Addressing of the accessible registers of the Serial Port is shown below (Table 4). The base addresses of the serial
ports are defined by the configuration registers (see section CONFIGURATION on page 45). The Serial Port
registers are located at sequentially increasing addresses above these base addresses. The SP37E760 contains two
serial ports, each of which contain a register set as described below.
Table 4 - Addressing the Serial Port
A1
A0
0
0
Receive Buffer (read)
0
0
Transmit Buffer (write)
0
1
Interrupt Enable (read/write)
1
0
Interrupt Identification (read)
1
0
FIFO Control (write)
1
1
Line Control (read/write)
0
0
Modem Control (read/write)
0
1
Line Status (read/write)
1
0
Modem Status (read/write)
1
1
Scratchpad (read/write)
0
0
Divisor LSB (read/write)
0
1
Divisor MSB (read/write)
Note
1
:
DLAB is Bit 7 of the Line Control Register
DLAB
1
0
0
0
X
X
X
X
X
X
X
1
1
A2
0
0
0
0
0
0
1
1
1
1
0
0
REGISTER NAME
4.1.1
The Receive Buffer register (Address Offset = 0H, DLAB = 0, READ ONLY) holds the received incoming data byte.
Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an
additional shift register to receive the serial data stream and convert it to a parallel 8 bit character which is transferred
to the Receive Buffer register. The shift register is not accessible.
RECEIVE BUFFER REGISTER (RB)
4.1.2
The Transmit Buffer register (Address Offset = 0H, DLAB = 0, WRITE ONLY) contains the data byte to be
transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the
8 bit data character to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of
the previous byte is complete.
TRANSMIT BUFFER REGISTER (TB)
4.1.3
The lower four bits of the Interrupt Enable register (Address Offset = 1H, DLAB = 0, READ/WRITE) control the
enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by
resetting bits 0 through 3 of this register. Similarly, by setting the appropriate bits of this register to a high selected
interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any
Serial Port interrupt out of the SP37E760. All other system functions operate in their normal manner, including the
Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below.
INTERRUPT ENABLE REGISTER (IER)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP8720 | ECL two-modulus divider, with ECL10K compatible outputs |
| SP8720ADG | ECL two-modulus divider, with ECL10K compatible outputs |
| SP8720BDG | ECL two-modulus divider, with ECL10K compatible outputs |
| SPF5001 | Surface-mount 4-circuit Low-side Switch Array |
| SPF5002 | Surface-mount 4-circuit Low-side Switch Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP37E760-MD | 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| SP37E760-MT | 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| SP37R0FL | 制造商:TE Connectivity 功能描述:SP3 7R0 1% LOOSEFixed Resistor |
| SP38 | 制造商:BES 功能描述:3/8" x 6" Spade Bit 制造商:BES MANUFACTURING 功能描述:SPADE BIT 3/8 X 6 INCH |
| SP380 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NOR GATES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。