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| 型號(hào)： | SP37E760-MC |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁(yè)數(shù)： | 33/78頁(yè) |
| 文件大?。?/td> | 510K |
| 代理商： | SP37E760-MC |
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SMSC DS – SP37E760
Rev. 04/13/2001
5.4 EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of which are listed below. The individual features are explained in
greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel
Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
5.4.1
The following terms are used in this document:
assert
When a signal asserts it transitions to a “true” state, when a signal deasserts it transitions to a “false”
state.
forward
Host to Peripheral communication.
reverse
Peripheral to Host communication.
Pword
A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8
bits.
1
A high level
0
A low level
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document:
IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.09, Jan 7, 1993. This document is
available from Microsoft. The bit map of the Extended Parallel Port registers is shown in Table 16.
Table 16 - ECP Registers
D7
D6
D5
data
PD7
PD6
PD5
ecpAFifo
2
Addr/RLE
dsr
1
nBusy
nAck
PError
dcr
1
0
0
Direction
VOCABULARY
D4
PD4
Address or RLE field
Select
ackIntEn
D3
PD3
D2
PD2
D1
PD1
D0
PD0
nFault
SelectIn
0
0
0
nInit
autofd strob
e
cFifo
2
ecpDFifo
2
tFifo
2
cnfgA
cnfgB
ecr
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
1
0
nErrIntrEn
0
0
0
0
0
0
0
0
0
0
full
0
0
compress
intrValue
MODE
dmaEn
serviceIntr
empt
y
Note
1
Note
2
These registers are available in all modes.
All FIFOs use one common 16 byte FIFO.
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| SP37E760-MD | 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| SP37E760-MT | 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| SP37R0FL | 制造商:TE Connectivity 功能描述:SP3 7R0 1% LOOSEFixed Resistor |
| SP38 | 制造商:BES 功能描述:3/8" x 6" Spade Bit 制造商:BES MANUFACTURING 功能描述:SPADE BIT 3/8 X 6 INCH |
| SP380 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NOR GATES |
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