參數(shù)資料
型號(hào)： SN74LVT8980FK
廠商： Texas Instruments, Inc.
英文描述： EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
中文描述： 嵌入式測(cè)試總線控制器IEEE標(biāo)準(zhǔn)1149.1 JTAG接口，8咨詢大師比特通用主機(jī)接口
文件頁(yè)數(shù)： 6/34頁(yè)
文件大?。?/td> 495K
代理商： SN74LVT8980FK
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
application information (continued)
The eTBC also provides several capabilities that support special target application requirements. The eTBC’s
test-output enable allows its master function to be disabled so that another device (an external tester, for
example) can control the target TAP. Where required, due to target non-compliance or sensitivity to state
sequencing, discrete-control mode provides the host software with arbitrary control of TMS and TDO
sequences. Also, where targets may be sensitive to leaving Shift-DR state during scan operation, gated-TCK
mode allows the TCK output to be stopped, rather than cycling the target TAP state to Pause-DR state, when
service to TDI buffer or TDO buffer is required.
Where target devices are extremely distant (due to cabling, etc.), pipelining may be implemented at intervals
along the incoming or outgoing paths to retime (deskew) the TDI, TDO, and TMS signals. An example is shown
in Figure 2. In such applications, the eTBC can automatically adjust the incoming test-data bit stream to account
for cycle delays introduced by the pipeline.
TDI
TDO
TMS
TCK
’LVT8980
eTBC
1D
1D
1D
C1
Distant
IEEE
Std
1149.1-
Compliant
Device
Chain
Figure 2. Retimed Interface to Target
Also, in gated-TCK mode, special scan commands provide transparent support for addressable shadow
protocols. Thus, in conjunction with its high-drive outputs, the eTBC can fully support multidrop backplane TAP
configurations implemented with TI’s addressable scan ports (ASP). Figure 3 shows a multidrop TAP
configuration in a passive-backplane application implemented with a centralized (one eTBC per chassis/rack)
test-control architecture, while Figure 4 shows a passive-backplane application implemented with a distributed
(eTBC per module) test-control architecture. Figure 5 shows a multidrop TAP configuration in an
active-backplane (motherboard) application.
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