參數(shù)資料
型號(hào)： SN74LVT8980FK
廠商： Texas Instruments, Inc.
英文描述： EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
中文描述： 嵌入式測(cè)試總線控制器IEEE標(biāo)準(zhǔn)1149.1 JTAG接口，8咨詢大師比特通用主機(jī)接口
文件頁(yè)數(shù)： 13/34頁(yè)
文件大?。?/td> 495K
代理商： SN74LVT8980FK
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 2. ConfigurationA Register Decode
CONFIGURATIONA
BIT
GROUP
BIT NO.
VALUE
RESULT
NTOE
5
0
TAP outputs (TCK, TDO, TMS, TRST) are enabled.
1
TAP outputs (TCK, TDO, TMS, TRST) are disabled (high impedance).
00
No loopback – TDI pin inputs to TDI buffer.
LPBK
4 3
4–3
01
TMS loopback – TAP-state generator inputs to TDI buffer. TMS and TDO pins are fixed high.
10
TDO loopback – TDO buffer inputs to TDI buffer. TMS and TDO pins are fixed high.
11
Reserved
000
Automatic/free-running-TCK mode – all TAP outputs are generated autonomously in the eTBC according
to the active command. The TCK output runs continuously; while operating a scan command, if the TDI
buffer becomes full and/or the TDO buffer becomes empty, the TAP state is cycled to Pause-DR or
Pause-IR, as appropriate, until the host performs the required buffer service.
Automatic/gated-TCK mode – all TAP outputs are generated autonomously in the eTBC according to the
active command. The TCK output is run only when required to move TAP state or to progress run-test or
scan operations, otherwise, it is gated off (low); while operating a scan command, if the TDI buffer
becomes full and/or the TDO buffer becomes empty, the TAP state remains in Shift-IR or Shift-DR, as
appropriate, but the TCK output is gated off until the host performs the required buffer service.
MODE
2–0
001
010
Discrete-control mode – all TAP outputs are determined by contents of the discrete-control register under
control of host software.
011–111
Reserved
Table 3. ConfigurationB Register Decode
CONFIGURATIONB
BIT
GROUP
BIT NO.
VALUE
RESULT
CDIV
7–5
000–111
TCK = (CLKIN)/(2CDIV); reset value TCK = (CLKIN)/(24) = CLKIN/16
RDLY
3–0
0000–11
11
Number of retiming delays to accommodate = RDLY; while operating a scan command, TDI sampling is
delayed by a number of TCK cycles, equal to RDLY, following the generation of Shift-DR or Shift-IR state,
as appropriate.
The negated test-output-enable (NTOE) bit allows the host to disable the TAP outputs via software in a manner
analogous to the hardware TOE. The loopback (LPBK) bit group allows the selection of the source of data to
be input to the TDI buffer – from the TDI pin for normal eTBC operations or, for eTBC verification purpose, from
TAP-state (TMS) generator or TDO buffer. The test mode (MODE) bit group provides a choice of
automatic/free-running-TCK, automatic/gated-TCK, or discrete-control modes.
The clock-divisor (CDIV) bit group allows software control of the TCK output frequency based on a division of
the CLKIN input. Divisors from 2
0
(1) to 2
7
(128) are provided. The clock divisor defaults to 2
4
(16) on eTBC
reset (power-up, hardware-initiated, or software-initiated). The retiming-delay (RDLY) bit group provides for the
automatic accommodation of retiming (pipeline) delays, which can be used to deskew the TAP signals to target
scan chains that are electrically distant (due to cabling delays, etc).
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