- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365640 > SN74LVT8980FK (Texas Instruments, Inc.) EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES PDF資料下載
參數(shù)資料
| 型號： | SN74LVT8980FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES |
| 中文描述： | 嵌入式測試總線控制器IEEE標準1149.1 JTAG接口，8咨詢大師比特通用主機接口 |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 495K |
| 代理商： | SN74LVT8980FK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
status register
The status of the eTBC is fully reported and continuously updated in the status register. The decode of the
various bit groups assigned to the status register is given in Table 4.
Table 4. Status Register Decode
STATUS
BIT
GROUP
BIT NO.
VALUE
RESULT
TDIS
7
0
The TDI buffer is empty – no TDI data is available for host read.
1
The TDI buffer is not empty – at least one byte of TDI data is available for host read.
TDOS
6
0
The TDO buffer is not full – at least one byte in TDO buffer is available for host write.
1
The TDO buffer is full – no bytes in TDO buffer are available for host write.
CTRS
5
0
The counter is not loaded with a complete 32-bit value – command operation cannot begin until counter
load completes.
1
The counter is loaded with a complete 32-bit value – command operation can begin.
0000
The current target TAP state (as sent by eTBC) is Test-Logic-Reset.
0001
The current target TAP state (as sent by eTBC) is Select-DR-Scan.
0010
The current target TAP state (as sent by eTBC) is Capture-DR.
0011
The current target TAP state (as sent by eTBC) is Shift-DR.
0100
The current target TAP state (as sent by eTBC) is Exit1-DR.
0101
The current target TAP state (as sent by eTBC) is Pause-DR.
0110
The current target TAP state (as sent by eTBC) is Exit2-DR.
TAPST
3 0
3–0
0111
The current target TAP state (as sent by eTBC) is Update-DR.
1000
The current target TAP state (as sent by eTBC) is Run-Test/Idle.
1001
The current target TAP state (as sent by eTBC) is Select-IR-Scan.
1010
The current target TAP state (as sent by eTBC) is Capture-IR.
1011
The current target TAP state (as sent by eTBC) is Shift-IR
1100
The current target TAP state (as sent by eTBC) is Exit1-IR.
1101
The current target TAP state (as sent by eTBC) is Pause-IR.
1110
The current target TAP state (as sent by eTBC) is Exit2-IR.
1111
The current target TAP state (as sent by eTBC) is Update-IR.
The TDI-buffer-status (TDIS) bit reports the readiness of the TDI buffer to respond to a host read. The
TDO-buffer-status (TDOS) bit reports the readiness of the TDO buffer to respond to a host write. The
counter-status (CTRS) bit reports the readiness of the counter to support a command that uses the counter. The
current-TAP-state (TAPST) bit group continuously reports the target TAP state as monitored by the eTBC.
command register
The command register is used to perform software reset of the eTBC, to discretely control the state of the TRST
output when not in discrete-control mode, and to initiate test operations in the target(s).The decode of the
various bits assigned to the command register is given in Table 5.
Any read to the command register while a command is in progress returns the value written to the command
register upon initiation of the command. Once a command finishes, the operation-code (OPCOD) bit group in
the command register is reset to null. In this way, the status of a requested command can be monitored/polled
by the host.
With the exception of the software-reset (SWRST) bit, which can be written at any time, writes to the command
register while a command is in progress causes RDY inactive and is ignored if the write cycle is terminated
before the previously requested command finishes.
相關PDF資料 |
PDF描述 |
|---|---|
| SN54LVT8980JT | EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES |
| SN54LVTH16245AWD | 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN54LVTH16543WD | XTAL MTL SMT HC49/USM |
| SN54LVTH16543 | Analog Multiplexers/Demultiplexers with Injection Current Effect Control; Package: PDIP-16; No of Pins: 16; Container: Rail; Qty per Container: 500 |
| SN74LVTH16543DGG | 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVT8986GGV | 功能描述:特定功能邏輯 3.3V Link Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8986PM | 功能描述:特定功能邏輯 3.3V Link Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8986ZGV | 功能描述:特定功能邏輯 Linking Addressable Scan Ports 3.3v RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8996DW | 功能描述:特定功能邏輯 3.3V 10-Bit Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8996DWR | 功能描述:特定功能邏輯 3.3V 10-Bit Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。