參數(shù)資料
型號(hào)： SN74LVT8980FK
廠商： Texas Instruments, Inc.
英文描述： EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
中文描述： 嵌入式測(cè)試總線控制器IEEE標(biāo)準(zhǔn)1149.1 JTAG接口，8咨詢大師比特通用主機(jī)接口
文件頁(yè)數(shù)： 24/34頁(yè)
文件大小： 495K
代理商： SN74LVT8980FK
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Shift-IR
For a target device, upon entry to the Shift-IR state, the instruction register is placed in the scan path between
TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state.
TDO outputs the logic level present in the least-significant bit of the instruction register. While in the stable
Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle.
Exit1-IR, Exit2-IR
For target devices, the
Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan.
It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction
register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.
Pause-IR
For target devices, no specific function is performed in the stable Pause-IR state, in which the TAP controller
can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without
loss of data.
Update-IR
For target devices, the current instruction is updated and takes effect on the falling edge of TCK, following entry
to the Update-IR state.
TDO buffer
The TDO buffer is the 4
×
8-bit-parallel-to-serial FIFO that accepts scan data from the host in 8-bit-parallel format
and serializes it onto the TDO pin during scan operations. Scan data is expected to be transferred from the host
in least-significant-byte-first order to meet IEEE Std 1149.1 requirements for least-significant-bit-first scan order.
Any partial byte to be written should be justified to D0. The TDO buffer is cleared upon command initiation, so
no scan data should be written to the TDO buffer before writing a scan command to the command register.
The TDO-buffer status (not full/full) is maintained in the status register (bit 6, TDOS). When the TDO-buffer
status is full, writes to the TDO buffer is held off by RDY inactive and if the write cycle is aborted prior to RDY
active, the write data is ignored.
For the convenience and efficiency of operating scans to the target for which outgoing data is not required, the
eTBC supports special classes of input-only and recirculate scan commands that do not require nor operate
the TDO buffer and so the host need not perform any write access to it. While the input-only scan commands
are operating, the TDO pin outputs a fixed high level. While the recirculate scan commands are operating, the
TDO pin recirculates to the target the data that is received at TDI.
While the eTBC is in discrete-control mode, the TDO buffer is not used; instead, the state of the TDO pin is
determined by the contents of the discrete-control register. Thus, TMS/TDO sequences that cannot be
automatically generated still can be applied through the eTBC to targets that require such (e.g., near-compliant
devices).
For eTBC verification/debugging, the TDO-buffer output can be selected for loopback into the TDI buffer. When
this TDO-loopback mode is selected, although a host-requested command executes in the eTBC, the target
is not affected, as both TMS and TDI are fixed at a high level.
Upon eTBC reset (power up, hardware initiated, or software initiated), the TDO buffer is cleared and assumes
its not-full state.
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