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| 型號： | SN74LVT8980FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES |
| 中文描述： | 嵌入式測試總線控制器IEEE標準1149.1 JTAG接口，8咨詢大師比特通用主機接口 |
| 文件頁數(shù)： | 31/34頁 |
| 文件大?。?/td> | 495K |
| 代理商： | SN74LVT8980FK |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
GND
500
500
Data Input
Timing Input
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: E. CL includes probe and jig capacitance.
F. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
G. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
H. The outputs are measured one at a time with one transition per measurement.
Open
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 10. Load Circuit and Voltage Waveforms (TCK, TDO, TMS, TRST Outputs)
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