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參數(shù)資料
| 型號(hào)： | SN74LVT8980FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES |
| 中文描述： | 嵌入式測(cè)試總線控制器IEEE標(biāo)準(zhǔn)1149.1 JTAG接口，8咨詢大師比特通用主機(jī)接口 |
| 文件頁數(shù)： | 2/34頁 |
| 文件大?。?/td> | 495K |
| 代理商： | SN74LVT8980FK |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The eTBC masters all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus – test
clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST). All
such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for
additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can
be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK
cycles; the eTBC automatically handles all associated serial-data justification.
Conceptually, the eTBC operates as a simple 8-bit memory- or I/O- mapped peripheral to a
microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBC via
its generic host interface, which includes an 8-bit data bus (D7–D0) and a 3-bit address bus (A2–A0). Read/write
select (R/W) and strobe (STRB) signals are implemented so that the critical host-interface timing is independent
of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into,
a host read/write cycle when the eTBC cannot respond immediately to the requested read/write operation.
High-level commands are issued by the host to cause the eTBC to generate the TMS sequences necessary
to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or
data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A
32-bit counter can be programmed to allow a predetermined number of scan or execute cycles.
During scan operations, serial data that appears at the TDI input is transferred into a serial-to-4
×
8-bit-parallel
first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream
up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to
eight bits at a time, to a 4
×
8-bit-parallel-to-serial FIFO write buffer.
In addition to such simple state-movement, scan, and run-test operations, the eTBC supports several additional
commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back
to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TI’s
addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller
host to monitor the TDO or TMS data streams output by the eTBC.
The eTBC’s flexible clocking architecture allows the user to choose between free-running (in which the TCK
always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move,
run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode is also available in which
the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host.
These features ensure that virtually any IEEE Std 1149.1 target device or device chain – even where such may
not fully comply to IEEE Std 1149.1 – can be serviced by the eTBC.
While most operations of the eTBC are synchronous to CLKIN, a test-output enable (TOE) is provided for output
control of the TAP outputs, and a reset (RST) input is provided for hardware reset of the eTBC. The former can
be used to disable the eTBC so that an external controller can master the associated IEEE Std 1149.1 test bus.
The SN54LVT8980 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LVT8980 is characterized for operation from –40
°
C to 85
°
C.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVT8986GGV | 功能描述:特定功能邏輯 3.3V Link Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8986PM | 功能描述:特定功能邏輯 3.3V Link Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8986ZGV | 功能描述:特定功能邏輯 Linking Addressable Scan Ports 3.3v RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8996DW | 功能描述:特定功能邏輯 3.3V 10-Bit Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVT8996DWR | 功能描述:特定功能邏輯 3.3V 10-Bit Add Port Multi-Add Tap Trncvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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