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| 型號： | SN54LVT8980JT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES |
| 中文描述： | 嵌入式測試總線控制器IEEE標準1149.1 JTAG接口，8咨詢大師比特通用主機接口 |
| 文件頁數(shù)： | 1/34頁 |
| 文件大?。?/td> | 495K |
| 代理商： | SN54LVT8980JT |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of Texas Instruments (TI) Broad
Family of Testability Products Supporting
IEEE Std 1149.1-1990 (JTAG) Test Access
Port (TAP) and Boundary-Scan Architecture
Provide Built-In Access to IEEE Std 1149.1
Scan-Accessible Test/Maintenance
Facilities at Board and System Levels
While Powered at 3.3 V, the TAP Interface is
Fully 5-V Tolerant for Mastering Both 5-V
and/or 3.3-V IEEE Std 1149.1 Targets
Simple Interface to Low-Cost 3.3-V
Microprocessors/Microcontrollers Via 8-Bit
Asynchronous Read/Write Data Bus
Easy Programming Via Scan-Level
Command Set and Smart TAP Control
Transparently Generate Protocols to
Support Multidrop TAP Configurations
Using TI’s Addressable Scan Port
Flexible TCK Generator Provides
Programmable Division, Gated-TCK, and
Free-Running-TCK Modes
Discrete TAP Control Mode Supports
Arbitrary TMS/TDI Sequences for
Non-Compliant Targets
Programmable 32-Bit Test Cycle Counter
Allows Virtually Unlimited Scan/Test Length
Accommodate Target Retiming (Pipeline)
Delays of Up to 15 TCK Cycles
Test Output Enable (TOE) Allows for
External Control of TAP Signals
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
at TAP Support Backplane Interface and/or
High Fanout
Package Options Include Plastic
Small-Outline (DW) Package, Ceramic Chip
Carriers (FK), and Ceramic 300-mil DIPs (JT)
description
The ’LVT8980 embedded test-bus controllers (eTBC) are members of the TI broad family of testability integrated
circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex
circuit assemblies. Unlike most other devices of this family, the eTBC is not a boundary-scannable device;
rather, its function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an
embedded host microprocessor/microcontroller. Thus, the eTBC enables the practical and effective use of the
IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and
configuration/maintenance facilities at board and system levels.
12 13 14 15 16 17 18
SN54LVT8980 . . . JT PACKAGE
SN74LVT8980 . . . DW PACKAGE
(TOP VIEW)
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3
2
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RDY
TDO
V
CC
NC
TCK
TMS
TRST
D1
D2
D3
NC
GND
D4
D5
SN54LVT8980 . . . FK PACKAGE
(TOP VIEW)
D
R
S
T
R
D
C
N
N
A
A
A
D
T
27 26
STRB
R/W
D0
D1
D2
D3
GND
D4
D5
D6
D7
CLKIN
A0
A1
A2
RDY
TDO
V
CC
TCK
TMS
TRST
TDI
RST
TOE
1
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NC – No internal connection
Copyright
1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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