參數(shù)資料
型號(hào)： SN54LVT8980JT
廠商： Texas Instruments, Inc.
英文描述： EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
中文描述： 嵌入式測(cè)試總線控制器IEEE標(biāo)準(zhǔn)1149.1 JTAG接口，8咨詢大師比特通用主機(jī)接口
文件頁(yè)數(shù)： 23/34頁(yè)
文件大?。?/td> 495K
代理商： SN54LVT8980JT
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Test-Logic-Reset
The eTBC TAP-state generator powers up in the Test-Logic-Reset state. Alternatively, the eTBC can be forced
to this state asynchronously by assertion of its RST input or synchronously by writing the eTBC command
register (bit 7-SWRST).
For a target device in the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal
logic function of the device is performed. The instruction register is reset to an opcode that selects the optional
IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their
power-up values.
Run-Test/Idle
For a target device, Run-Test/Idle is a stable state in which the test logic can be actively running a test or can
be idle.
Select-DR-Scan, Select-lR-Scan
For a target device, no specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the
TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either
data-register scan or instruction-register scan.
Capture-DR
For a target device in the Capture-DR state, the selected data register can capture a data value as specified
by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the Capture-DR
state is exited.
Shift-DR
For a target device, upon entry to the Shift-DR state, the selected data register is placed in the scan path
between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an
active state. TDO outputs the logic level present in the least-significant bit of the selected data register. While
in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
Exit1-DR, Exit2-DR
For a target device, the
Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is
possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.
Pause-DR
For target devices, no specific function is performed in the stable Pause-DR state. The Pause-DR state
suspends and resumes data-register scan operations without loss of data.
Update-DR
For a target device, if the current instruction calls for the selected data register to be updated with current data,
such update occurs on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
For a target device in the Capture-IR state, the instruction register captures its current status value. This capture
operation occurs on the rising edge of TCK, upon which the Capture-IR state is exited.
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