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參數(shù)資料
| 型號(hào)： | SN54LVT8980JT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES |
| 中文描述： | 嵌入式測(cè)試總線控制器IEEE標(biāo)準(zhǔn)1149.1 JTAG接口，8咨詢大師比特通用主機(jī)接口 |
| 文件頁(yè)數(shù)： | 33/34頁(yè) |
| 文件大?。?/td> | 495K |
| 代理商： | SN54LVT8980JT |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676C – DECEMBER 1996 – REVISED AUGUST 1997
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
considerations for migrating ’LVT8990 “X” die designs to ’LVT8980A
As noted above, device revision ’LVT8980A proposes to fix the two known silicon errata of ’LVT8980. It is
recommended that designs based on the ’LVT8980 “X” die consider and plan for migration to ’LVT8980A.
In the case of all known silicon errata items, the ’LVT8980A device function will be a super set of the actual
function of ’LVT8980 “X” die and will comply with the device descriptions and specifications of this data sheet.
So, with respect to the proposed fixes, ’LVT8980JA can directly replace ’LVT8980 “X” die in existing designs.
However, the ’LVT8980A device revision proposes to make an additional change that does not comply with the
device descriptions and specifications of this data sheet. This additional change is noted here.
item 1 – make TOE pin signal high enabling and rename to TOFF
The ’LVT8980A device revision proposes to modify the polarity of the TOE (active-low test output enable) pin
signal (pin 13 for DW, JT packages) to high enabling and consequently to rename the pin signal to active-low
test off (TOFF).
workaround
For an ’LVT8980 “X” die design, it is recommended that the TOE pin be tied off to ground via a discrete resistor.
Then, to migrate to use of ’LVT8980A device, the design need only be modified to omit the resistor – the internal
resistor at the ’LVT8980A TOFF pin will ensure that it is driven by default to the state required to enable the
device TAP outputs.
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