參數(shù)資料
型號(hào): SDA9401
廠商: Electronic Theatre Controls, Inc.
英文描述: Scan Rate Converter using Embedded DRAM Technology Units
中文描述: 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股
文件頁(yè)數(shù): 51/69頁(yè)
文件大?。?/td> 1142K
代理商: SDA9401
Micronas
51
Preliminary Data Sheet
SDA 9401
Subaddress 06
Bit
Name
Function
D7...D0
OPDEL
Output processing delay (in number of lines):
Delay(VIN to VOUT) = (OPDEL + 1) * Tline [OPDEL = 170]
Subaddress 07
Bit
Name
Function
D7...D0
VERWIDTH
Vertical width of inserted picture in input lines:
Vertical width = (2 * VERWIDTH) [VERWIDTH = 0]
Subaddress 08
Bit
Name
Function
D7...D0
VERPOS
Vertical position of inserted picture in input lines:
Vertical position = (2 * VERPOS) + NALIP + 3 [VERPOS = 0]
Subaddress 09
Bit
Name
Function
D7...D2
HORWIDTH
Horizontal width of inserted picture in system clocks of CLK1:
Horizontal width = (32 * HORWIDTH) [HORWIDTH = 0]
PLL1 range, only for test purposes [PPL1RA=0]
D1...D0
PLL1RA(1...0)
Subaddress 0A
Bit
Name
Function
D7...D2
HORPOS
Horizontal position of inserted picture in system clocks of CLK1:
Horizontal position = (32 * HORPOS) + (4 * NAPIPDL + NAPIPPH + 8)
[HORPOS = 0]
PLL1 range, only for test purposes [PPL1RA=0]
D1...D0
PLL1RA(3...2)
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