參數(shù)資料
型號(hào): SDA9401
廠商: Electronic Theatre Controls, Inc.
英文描述: Scan Rate Converter using Embedded DRAM Technology Units
中文描述: 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股
文件頁(yè)數(shù): 41/69頁(yè)
文件大?。?/td> 1142K
代理商: SDA9401
SDA 9401
Micronas
41
Preliminary Data Sheet
X
ab:
X: signal component a: sample number b: bit number
6.7
High data rate processing (HDR)
The output signal can be vertically expanded. The expansion as well as the different scan rate
conversion algorithms are processed in the HDR block. For the vertical expansion line memories
are used. If the operation frequency X1/CLK2 is higher than 27 MHz plus 10%, the line memories
will not work correctly any more. In this case only simple processing will be possible. Simple
processing means, that the vertical expansion must be disabled.
The table below defines the internal expansion factor ZOOM depending on the RMODE and
VERINT parameter.
Output write parameter: VERINT
The reachable expansion factors are listed in the table below in case of VDECON=0 and
VDECON=2 (vertical compression of the input signal with factor 1.0 and 1.5).
UVIN7 U
07
UVIN6 U
06
UVIN5 U
05
UVIN4 U
04
UVIN3 U
03
UVIN2 U
02
UVIN1 U
01
UVIN0 U
00
V
07
V
06
V
05
V
04
V
03
V
02
V
01
V
00
VERINT
RMODE
ZOOM
I2C-bus
parameter
I2C-bus
parameter
0
2*(VERINT+1)
1
(VERINT+1)
Data
Pin
4:2:2 Parallel
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