參數(shù)資料
型號(hào)： SAA6721E
廠商： NXP SEMICONDUCTORS
元件分類： 圖形處理器
英文描述： SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù)： 58/72頁(yè)
文件大?。?/td> 360K
代理商： SAA6721E
1999 May 11
58
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
8.12
Temporal dithering (frame rate controller)
The SAA6721E is able to display true colour (8 bits per
colour) on high colour displays (6 bits per colour).
The algorithm used is temporal dithering. This feature can
be enabled by setting frc_on to logic 1 in the general
configuration register block (see Table 7).
8.13
Output interface
8.13.1
G
ENERAL
The output interface is the interface between the
SAA6721E and the TFT panel. Its timing parameters can
be programmed in a wide range to support panels of many
different manufacturers.
The output interface can operate in two different modes.
The first mode is the free running mode which is adapted
to the memory mode of the SAA6721E. In this mode the
output is independent from the input at the RGB/YUV input
interface. So the output frame generation can start directly
after releasing the internal reset. For getting a high frame
rate the output timing can be programmed to satisfy the
minimum timing requirements of the panel.
Fig.21 Character matrix organization.
MHB261
handbook, halfpage
1 byte
(a)
(b)
a: 24
×
24 font definition.
b: 12
×
16 font definition.
The second mode is synchronized to the input data, mainly
implemented to support the SAA6721E’s no memory
mode. In this mode the input data is sent directly to the
output interface, which must synchronize its output timing
to get the same frame rate as the input. Additionally it
starts generating vertical blanking and synchronization
signals at pins PVS and PHS directly after releasing the
internal reset.
After the programmed top blanking the output interface
enlarges the last blanking line until data from the input
interface reaches the output interface. Because too long
lines cause counter overflows in the panels, a controlling
mechanism exists which changes the length of the
blanking, border and active lines according to the timing
requirements of the panel and the applied graphics mode.
This mode can be enabled by setting the programming
register sync_mode to logic 1, otherwise the first free
running mode will be selected.
The length controlling the blanking, border and active
video region can be enabled by asserting blank_ctrl,
border_ctrl, and active_ctrl.
The output interface also supports a Power-down mode
which sets all output signals to logic 0. This will be
activated by the programming flag power_down
(see section general configuration Table 7).
For flicker free switching between different input modes,
the output interface is able to set all data outputs to the
panel to logic 0, resulting in a black picture. Even if during
programming and internal reset no synchronization pulses
for the panel are generated and the panel loses the last
picture information, the panel still displays black colour,
because this is its Idle state. To switch the output interface
into this mode blank_tft must be set.
To enable the panel interface it must be enabled with
out_if_enable. The interface supports single pixel (24 bits)
and double pixel (48 bits) output in parallel. The selection
between these two modes must be done with
single_pixel_output. The active clock edge at PCLK can
also be selected by clk_pol.
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