參數(shù)資料
型號(hào)： SAA6721E
廠商： NXP SEMICONDUCTORS
元件分類： 圖形處理器
英文描述： SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù)： 3/72頁(yè)
文件大小： 360K
代理商： SAA6721E
1999 May 11
3
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
1
FEATURES
1.1
RGB video input
Digital single (24-bit) or dual (48-bit) channel RGB input
Data input of sampled RGB data with a pixel frequency
of maximum 150 MHz
Free definable data acquisition offsets and vertical
window size in single pixel increments, horizontal
window size in double pixel increments
Programmable pulses for ADC clamping and ADC gain
correction
Detection of presence of sync signals, and of their
polarities
Support for auto-adjustment functions for sample clock
frequency, phase, vertical and horizontal sample offset,
as well as colour adjustment
Maximum supported resolution of 1280
×
1024 dots
Super Extended Graphics Adapter (SXGA)
Support for detection of the applied graphics mode
(multi-sync).
1.2
YUV video input
Pin sharing between YUV and RGB input port
YUV 4 : 4 : 4, YUV 4 : 2 : 2, YUV 4 : 2 : 2 with CCIR 656
codes, YUV 4 : 1 : 1 input of interlaced and
non-interlaced digital video data
Maximum picture resolution of 1024
×
1024 pixels for
interlaced or non-interlaced video
Input of video data at maximum 75 MHz
Free definable data acquisition offsets and window in
double pixel or single line increments
YUV to RGB colour space conversion.
1.3
Video processing
Colour correction Look-Up Table (LUT)
Phase correct up and downscaling of the RGB data
Fully programmable scaling ratios
Independent horizontal and vertical scaling engine
Free definable position of the scaled input picture inside
the output picture with programmable border colour
De-interlacing unit for digital YUV video data
Zoom up to full-screen resolution of the de-interlaced
YUV video stream via the main scaler.
1.4
On screen display
Character based internal On Screen Display (OSD)
Programmable character matrix sizes of either
24
×
24 pixels (42 characters available) or
12
×
16 pixels (128 characters available)
Programmable width and height of the OSD window,
built from maximum 1152 characters
8 different colours for foreground and background
inclusive transparent colours
Overlay port for external OSD controller.
1.5
Video output
Single pixel/clock (24-bit) or double pixel/clock (48-bit)
digital RGB output
Generation of synchronization and validation signals for
the Thin Film Transistor (TFT) display
Frame rate control (temporal dithering) for displaying
true colour graphics on high colour displays
Free programmable timing for displays of several
manufacturers.
1.6
Memory interface
Support of both 1M
×
16 SDRAM, 256k
×
32 SGRAM or
128k
×
32 SGRAM devices
Maximum memory clock frequency of 125 MHz
Scalable memory size built of either 2, 3 or 4 SDRAM,
or of 1 or 2 SGRAM devices
Special mode for operation without external memory.
1.7
Miscellaneous
Internal Phase-Locked Loop (PLL) for memory and
panel clock generation from the system clock
I
2
C-bus interface with 2 selectable addresses
Boundary scan test circuit and Joint Test Action Group
(JTAG) test controller.
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