- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372112 > SAA6721E (NXP SEMICONDUCTORS) SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎) PDF資料下載
參數(shù)資料
| 型號(hào)： | SAA6721E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 圖形處理器 |
| 英文描述： | SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎) |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 33/72頁 |
| 文件大?。?/td> | 360K |
| 代理商： | SAA6721E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
1999 May 11
33
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
I
NTERLACED MODE PROGRAMMING
YUV CREF polarity
YUV clock qualifier is active LOW
YUV clock qualifier is active HIGH
YUV HREF polarity
Active data qualifier is active LOW
Active data qualifier is active HIGH
YUV format
CCIR 656
4 : 1 : 1 format
4 : 2 : 2 format
4 : 4 : 4 format
YUV field sampling mode
All incoming frames are captured
Capture alternating fields only
Capture odd fields only
Capture even fields only
Field reverse flag
Keep original odd field identification
Change field identification
34
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D3 and D2
D3 = 0 and D2 = 0
D3 = 0 and D2 = 1
D3 = 1 and D2 = 0
D3 = 1 and D2 = 1
D5 and D4
D5 = 0 and D4 = 0
D5 = 0 and D4 = 1
D5 = 1 and D4 = 0
D5 = 1 and D4 = 1
D6
logic 0
logic 1
V
ERTICAL SAMPLE OFFSET
Vertical sample offset from Vsync
35 and 36
W
D10 to D0
H
ORIZONTAL SAMPLE OFFSET
Horizontal sample offset from Hsync
37 and 38
W
D11 to D0
V
ERTICAL SAMPLE LENGTH
Vertical sample window length
39 and 40
W
D10 to D0
H
ORIZONTAL SAMPLE LENGTH
Horizontal sample window length
41 and 42
W
D11 to D0
C
LAMP PULSE START
Start of clamp pulse after active edge of Hsync
43
W
D7 to D0
C
LAMP PULSE END
End of clamp pulse after active edge of Hsync
44
W
D7 to D0
G
AIN CORRECTION PULSE START DELAY
Delay of start of GAINC pulse from first edge of Hsync
45
W
D7 to D0
G
AIN CORRECTION PULSE END DELAY
Delay of end of pulse GAINC from second edge of Hsync
46
W
D7 to D0
NAME
SUBADDRESS
R/W
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6750 | Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA7102 | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:12; Connector Shell Size:28; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| SAA7102E | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103,557 | 功能描述:IC AUD/VID ENCODER MPEG 208-SQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。