參數(shù)資料
型號(hào)： SAA6721E
廠商： NXP SEMICONDUCTORS
元件分類： 圖形處理器
英文描述： SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁(yè)數(shù)： 46/72頁(yè)
文件大?。?/td> 360K
代理商： SAA6721E
1999 May 11
46
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
8.3
RGB/YUV input interface
8.3.1
S
AMPLING MODE
The input interface allows sampling of RGB or YUV data.
Because of that two different modes must be supported:
RGB data sampling and YUV data sampling. The flag
rgb_proc_on selects RGB mode sampling if asserted.
If the flag is not asserted YUV data is selected.
Sampling of interlaced RGB data is enabled by
rgb_interl_on.
8.3.2
RGB
DATA SAMPLING
Sampling is done on the rising edge or on both edges of
VCLK depending on the number of ADCs.
The sample window is defined by v_offset, h_offset,
v_length, and h_length.
The offset counters start counting from the second edge of
their reference signals, i.e. VVS for vertical offset and VHS
for horizontal offset. Figure 13 shows the horizontal offset.
The polarities of the sync signals are given with vs_pol and
hs_pol. The vertical sample offset is given in lines and the
horizontal offset is measured in pixels. The width of the
sample window is defined by the length counters.
The vertical width is measured in lines and the horizontal
width in pixels, but only even pixel numbers are allowed.
The sample clock for the ADCs is always VCLK, but in dual
ADC mode this clock is half the pixel clock. Because of
that, in dual ADC mode, both clock edges are used to
sample data by the ADCs.
Table 10
Clock relationships
In single ADC mode, with each VCLK clock, a pixel must
be sampled from port A. In dual ADC mode, at each VCLK
clock edge, a pixel must be sampled alternating from
port A or B. The flag adc_sample_seq selects from which
port data sampling starts after the active edge of the
horizontal synchronization pulse.
8.3.3
C
LAMP PULSE GENERATION
The clamp pulse is generated with respect to half the dot
clock. The counters values responsible for switching the
clamp pulse on or off are clamp_on and clamp_off. Both
start counting from the second edge of VHS. The polarity
of CLAMP is given with clamp_pol.
NUMBER OF
ADCs
VCLK
VCLK
SAMPLE EDGE
1
2
dot clock
1
2
dot clock
positive
both
Fig.13 RGB data sampling.
handbook, full pagewidth
MHB253
VHS
RGB data
h_offset
h_length
0
1
2
3
4
5
n
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