參數(shù)資料
型號(hào)： SAA6721E
廠商： NXP SEMICONDUCTORS
元件分類： 圖形處理器
英文描述： SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁數(shù)： 44/72頁
文件大?。?/td> 360K
代理商： SAA6721E
1999 May 11
44
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
8.2.2
C
LOCK DIVIDER
The pre- and post-dividers are implemented in such a way, that they support dividing ratios of 0.5 steps in an interval
from 1.5 to 10.5. All further dividing ratios are in steps of 1.0; see Fig.12 and Table 9.
Programming of the clock dividers must be done using the registers 26 to 32. It is necessary that the clock dividers must
be disabled before programming and be enabled afterwards. This can be done with pre_div_enable and
post_div_enable.
Table 9
Clock divider programming
RATIO
P-COUNTER
(HEX)
N-COUNTER
(HEX)
N-OFFSET
COUNTER (HEX)
HALF CLK
1.5
2.0
2.5
3.0
3.5
10
00
30
10
41
10
00
30
10
41
1
0
2
0
3
1
0
1
1
1
Fig.11 Clock generator.
handbook, full pagewidth
MHB251
PLL
×
32
PRE-DIVIDER
POST-DIVIDER
÷
2
MCLKO
PCLK
MCLKI
CLK
Fig.12 Clock waveforms.
handbook, full pagewidth
MHB252
CLK/4
CLK/5
CLK/4.5
CLK/5.5
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