參數(shù)資料
型號： SAA6721E
廠商： NXP SEMICONDUCTORS
元件分類： 圖形處理器
英文描述： SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎)
中文描述： GRAPHICS PROCESSOR, PBGA292
封裝： 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁數(shù)： 18/72頁
文件大小： 360K
代理商： SAA6721E
1999 May 11
18
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
Table 4
SDRAM channel configurations
Notes
1.
2.
36 MHz clock frequency.
50 MHz clock frequency.
INPUT
RESOLUTION
SVGA (800
×
600)
XGA (1024
×
768)
SXGA (1280
×
1024)
60 Hz
75 Hz
60 Hz
75 Hz
60 Hz
75 Hz
Panel
XGA
(1)
2 Mbits frame buffer needed
288 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
307 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
3 Mbits frame buffer needed
411 Mbits/s
bandwidth;
2
×
HSC or
3
×
MSC
435 Mbits/s
bandwidth;
2
×
HSC or
3
×
MSC
4 Mbits frame buffer needed
475 Mbits/s
bandwidth;
3
×
HSC or
3
×
MSC
624 Mbits/s
bandwidth;
3
×
HSC or
4
×
MSC
319 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
337 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
452 Mbits/s
bandwidth;
2
×
HSC or
3
×
MSC
476 Mbits/s
bandwidth;
3
×
HSC or
3
×
MSC
540 Mbits/s
bandwidth;
3
×
HSC or
3
×
MSC
705 Mbits/s
bandwidth;
4
×
HSC or
4
×
MSC
SXGA
(2)
7.6.2
SGRAM
MEMORY CONFIGURATION
SGRAM devices organized to 256k
×
32 bits are available,
and feature the wide data bus for high speed applications.
With these devices a frame buffer can be built, without
wasting memory because of bandwidth. In case of
SGRAM usage, the memory data bus of the SAA6721E
can be split into 2 channels of 32 bits each.
Each channel gives, in HSC mode with 125 MHz clock
frequency, an effective bandwidth of 456 Mbits/s; and in
MSC mode, with 100 MHz clock speed, an effective
bandwidth of 364 Mbits/s.
Table 5 gives the channel configuration for several input
and panel resolutions.
Table 5
SGRAM channel configurations
Notes
1.
2.
36 MHz clock frequency.
50 MHz clock frequency.
INPUT
RESOLUTION
SVGA (800
×
600)
XGA (1024
×
768)
SXGA (1280
×
1024)
60 Hz
75 Hz
60 Hz
75 Hz
60 Hz
75 Hz
Panel
XGA
(1)
2 Mbits frame buffer needed
288 Mbits/s
bandwidth;
1
×
HSC or
1
×
MSC
307 Mbits/s
bandwidth;
1
×
HSC or
1
×
MSC
3 Mbits frame buffer needed
411 Mbits/s
bandwidth;
1
×
HSC or
2
×
MSC
435 Mbits/s
bandwidth;
1
×
HSC or
2
×
MSC
4 Mbits frame buffer needed
475 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
624 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
319 Mbits/s
bandwidth;
1
×
HSC or
1
×
MSC
337 Mbits/s
bandwidth;
1
×
HSC or
1
×
MSC
452 Mbits/s
bandwidth;
1
×
HSC or
2
×
MSC
476 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
540 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
705 Mbits/s
bandwidth;
2
×
HSC or
2
×
MSC
SXGA
(2)
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