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參數(shù)資料
| 型號(hào)： | S71WS512N80BFIZZ0 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 91/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BFIZZ0 |
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
91
A d v a n c e I n f o r m a t i o n
Notes:
1. RDY active with data (DQ8 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (DQ8 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the
Boundary Crossing bit (DQ14) in the Configuration Register is set to 0
Figure 28. Latency with Boundary Crossing when Frequency > 66 MHz
Notes:
1. RDY active with data (DQ8 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (DQ8 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the
Boundary Crossing bit (DQ14) in the Configuration Register is set to 0
Figure 29. Latency with Boundary Crossing into Program/Erase Bank
CLK
Address (hex)
C124
C125
C126
C127
C127
C128
C129
C130
C131
D124
D125
D126
D127
D128
D129
D130
(stays high)
AVD#
RDY(1)
Data
OE#,
CE#
(stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C
7D
7E
7F
7F
80
81
82
83
latency
RDY(2)
latency
tRACC
tRACC
tRACC
tRACC
CLK
Address (hex)
C124
C125
C126
C127
C127
D124
D125
D126
D127
Read Status
(stays high)
AVD#
RDY(1)
Data
OE#,
CE#
(stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C
7D
7E
7F
7F
latency
RDY(2)
latency
tRACC
tRACC
tRACC
tRACC
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| S71WS512N80BFIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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